Patent US6028812A successfully refreshed from Google Patents.
US6028812A
Expired / Lapsed
US
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Semiconductor memory device and method for controlling the same
Assignee: Sharp Corp
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Filing: 1999-03-03
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Granted: 2000-02-22
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Expires: 2019-03-03
Abstract
Abstract A semiconductor memory device includes at least two memory cells included in a first bank; at least two word lines; and a first sensing amplifier and a second sensing amplifier. The first sensing amplifier amplifies and holds data of one of the memory cells connected to one of the word lines. The second sensing amplifier amplifies and holds data of one other memory cell connected to one other word line.
Inventors
- 👤 Hidehiko Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:43
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065; G11C7/10; G11C7/1015; G11C7/1042
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
72 words
A semiconductor memory device, comprising: at least two memory cells included in a first bank; at least two word lines; and a first sensing amplifier and a second sensing amplifier, wherein: the first sensing amplifier amplifies and holds data of one of the memory cells connected to one of the word lines, and the second sensing amplifier amplifies and holds data of one other memory cell connected to one other word line.
Claim 2
Dependent Claim
72 words
A semiconductor memory device, comprising: at least two memory cells included in a first bank; at least two word lines; and a first sensing amplifier and a second sensing amplifier, wherein: the first sensing amplifier amplifies and holds data of one of the memory cells connected to one of the word lines, and the second sensing amplifier amplifies and holds data of one other memory cell connected to one other word line.
Claim 3
Dependent Claim
14 words
A semiconductor memory device according to claim 1, which is synchronized with a clock.
Claim 4
Dependent Claim
56 words
A semiconductor memory device according to claim 1, further comprising: a first switch for electrically connecting and disconnecting the memory cell connected to the one word line and the first sensing amplifier; and a second switch for electrically connecting and disconnecting the memory cell connected to the one other word line and the second sensing amplifier.
Claim 5
Dependent Claim
33 words
A semiconductor memory device according to claim 1, further comprising at least two memory cells included in a second bank, wherein the first bank and the second bank share the second sensing amplifier.
Claim 6
Dependent Claim
53 words
A semiconductor memory device according to claim 1, further comprising: a column address counter for counting an address in synchronization with a falling edge of a column address strobe signal/CAS; and a column decoder for selecting a column in the first bank in accordance with an output signal from the column address counter.
Claim 7
Dependent Claim
46 words
A semiconductor memory device according to claim 2, further comprising: a column address counter for counting an address in synchronization with the clock; and a column decoder for selecting a column in the first bank in accordance with an output signal from the column address counter.
Claim 8
Dependent Claim
61 words
A semiconductor memory device according to claim 3, further comprising: a third switch for connecting and disconnecting the first sensing amplifier and a first data bus; a fourth switch for connecting and disconnecting the second sensing amplifier and a second data bus; and an input/output circuit, connected to the first data bus and the second data bus, for outputting the data.
Claim 9
Dependent Claim
78 words
A semiconductor memory device according to claim 7, wherein: the at least two memory cells are connected to a first bit line and a second bit line; the first bit line and the second bit line are connected to a first sense line and a second sense line through the first switch, and the first bit line and the second bit line are connected to a third sense line and a fourth sense line through the second switch.
Claim 10
Independent Claim
459 words
A method for controlling a semiconductor memory device including a plurality of memory cells included in one bank and arranged in a matrix, first and second amplifiers, first through fourth switches, first and second word lines, first and second bit lines, first through fourth sense lines, and first and second data buses, the method comprising the steps of: putting the first switch into a conducting state and putting the second switch into a non-conducting state when the first word line is selected after a first active command is input; activating only the first sensing amplifier connected to the first and second sense lines which are connected to the first and second bit lines through the first switch in a conducting state after the first word line is selected, thereby causing the first sensing amplifier to amplify a potential difference between the first and second sense lines and to latch data indicating the amplified potential difference: deselecting the first word line to rewrite the data into a memory cell while the first sensing amplifier latches the data after a read command is input; putting the first and second switches into a non-conducting state to precharge the first and second bit lines separated from the first and second sensing amplifiers; reading the data from the first sensing amplifier to the first data bus through the third switch; putting the second switch to a conducting state while the data is being read to the first data bus, to precharge the first and second bit lines and the third and fourth sense lines connected to the first and second bit lines; putting the first switch into a non-conducting state and putting the second switch into a conducting state when the second word line is selected after a second active command is input; activating only the second sensing amplifier connected to the third and fourth sense lines which are connected to the second switch, thereby causing the second sensing amplifier to amplify a potential difference between the third and fourth sense lines and to latch data indicating the amplified potential difference; deselecting the second word line to rewrite the data into a memory cell while the second sensing amplifier latches the data after a read command is input; putting the first and second switches into a non-conducting state, to precharge the first and second bit lines separated from the first and second sensing amplifiers; reading the data from the second sensing amplifier to the second data bus through the fourth switch; and putting the first switch into a conducting state while the data is being read to the second data bus, to precharge the first and second bit lines and the first and second sense lines connected to the first and second bit lines.
Claim 11
Independent Claim
459 words
A method for controlling a semiconductor memory device including a plurality of memory cells included in one bank and arranged in a matrix, first and second amplifiers, first through fourth switches, first and second word lines, first and second bit lines, first through fourth sense lines, and first and second data buses, the method comprising the steps of: putting the first switch into a conducting state and putting the second switch into a non-conducting state when the first word line is selected after a first active command is input; activating only the first sensing amplifier connected to the first and second sense lines which are connected to the first and second bit lines through the first switch in a conducting state after the first word line is selected, thereby causing the first sensing amplifier to amplify a potential difference between the first and second sense lines and to latch data indicating the amplified potential difference: deselecting the first word line to rewrite the data into a memory cell while the first sensing amplifier latches the data after a read command is input; putting the first and second switches into a non-conducting state to precharge the first and second bit lines separated from the first and second sensing amplifiers; reading the data from the first sensing amplifier to the first data bus through the third switch; putting the second switch to a conducting state while the data is being read to the first data bus, to precharge the first and second bit lines and the third and fourth sense lines connected to the first and second bit lines; putting the first switch into a non-conducting state and putting the second switch into a conducting state when the second word line is selected after a second active command is input; activating only the second sensing amplifier connected to the third and fourth sense lines which are connected to the second switch, thereby causing the second sensing amplifier to amplify a potential difference between the third and fourth sense lines and to latch data indicating the amplified potential difference; deselecting the second word line to rewrite the data into a memory cell while the second sensing amplifier latches the data after a read command is input; putting the first and second switches into a non-conducting state, to precharge the first and second bit lines separated from the first and second sensing amplifiers; reading the data from the second sensing amplifier to the second data bus through the fourth switch; and putting the first switch into a conducting state while the data is being read to the second data bus, to precharge the first and second bit lines and the first and second sense lines connected to the first and second bit lines.
Claim 12
Dependent Claim
22 words
A method for controlling a semiconductor memory device according to claim 9, wherein the semiconductor memory device is synchronized with a clock.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |