Patent US6026012A successfully refreshed from Google Patents.
US6026012A
Expired / Lapsed
US
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Dual port random access memory
Assignee: United Microelectronics Corp
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Filing: 1998-12-30
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Granted: 2000-02-15
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Expires: 2018-12-30
Abstract
Abstract A dual port random access memory (RAM). The dual port random access memory includes four N-MOS transistors and four P-MOS transistors. Both the N-MOS and the P-MOS transistors are used as pass gates. More specifically, two N-MOS transistors are used as pass gate for a set of bit lines and two P-MOS transistors are used as a pass gate to another set of bit lines.
Inventors
- 👤 C. C. Hsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:44
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
183 words
A dual port static random access memory, comprising: a first inverter, comprising a first input terminal and a first output terminal; a second inverter, comprising a second input terminal connecting to the first output terminal and a second output terminal connecting to the first input terminal; a first N-type MOS transistor, comprising a gate connecting to a first word line, a source/drain region connecting to a first bit line, and the other source/drain region connecting to the first output terminal; a second N-type MOS transistor, comprising a gate connecting to the first word line, a source/drain region connecting to a second bit line, and the other source/drain region connecting to the first input terminal; a first P-type MOS transistor, comprising a gate connecting to a second word line, a source/drain region connecting to a third bit line, and the other source/drain region connecting to the second input terminal; and a second P-type MOS transistor, comprising a gate connecting to the second word line, a sourice/drain region connecting to a fourth bit line, and the other source/drain region connecting to the second output terminal.
Claim 2
Dependent Claim
183 words
A dual port static random access memory, comprising: a first inverter, comprising a first input terminal and a first output terminal; a second inverter, comprising a second input terminal connecting to the first output terminal and a second output terminal connecting to the first input terminal; a first N-type MOS transistor, comprising a gate connecting to a first word line, a source/drain region connecting to a first bit line, and the other source/drain region connecting to the first output terminal; a second N-type MOS transistor, comprising a gate connecting to the first word line, a source/drain region connecting to a second bit line, and the other source/drain region connecting to the first input terminal; a first P-type MOS transistor, comprising a gate connecting to a second word line, a source/drain region connecting to a third bit line, and the other source/drain region connecting to the second input terminal; and a second P-type MOS transistor, comprising a gate connecting to the second word line, a sourice/drain region connecting to a fourth bit line, and the other source/drain region connecting to the second output terminal.
Claim 3
Dependent Claim
81 words
The dual port static random access memory according to claim 1, wherein the first inverter comprises: a third P-type MNOS transistors comprising a gate connecting to the first input terminal, a source/drain region connecting to a power source, and the other source/drain region connecting to the first output terminal; and a third N-type MOS transistor, comprising a gate connecting to the first input terminal, a source/drain region connecting to ground, and the other source/drain region connecting to the first output terminal.
Claim 4
Dependent Claim
82 words
The dual port static random access memory according to claim 2, wherein the second inverter comprises: a fourth P-type MOS transistor, comprising a gate connecting to the second input terminal, a source/drain region connecting to the power source, and the other source/drain region connecting to the second output terminal, and a fourth N-type MOS transistor, comprising a gate connecting to the second input terminal, a source/drain region connecting to the ground, and the other source/drain region connecting to the second output terminal.
Claim 5
Dependent Claim
261 words
A dual port static random access memory, comprising: a first N-type MOS transistor, comprising a gate connecting to a first word line, a source/drain region connecting to a first bit line, and the other source/drain region connecting to a first node: a second N-type MOS transistor, comprising a gate connecting to the first word line, a source/drain region connecting to a second bit line, and the other source/drain region connecting to a second node; a third N-type MOS transistor, comprising a gate connecting to the second node, a source/drain region connecting to ground, and the other source/drain region connecting to the first node; fourth N-type MOS transistor, comprising a gate connecting to the first node, a source/drain region connecting to the ground, and the other source/drain region connecting to the second node, a first P-type MOS transistor, comprising a gate connecting to a second word line, a source/drain region connecting to a third bit line, and the other source/drain region connecting to the first node; a second P-type MOS transistor, comprising a gate connecting to the second word line, a source/drain region connecting to a fourth bit line, and the other source/drain region connecting to the second node; a third P-type MOS transistor, comprising a gate connecting to the second node, a source/drain region connectinig to a power source, and the other source/drain region connecting to the first node; and a fourth P-type MOS transistor, comprising a gate connecting to the first node, a source/drain region connecting to the power source, and the other source/drain region connecting to the second node.
Claim 6
Dependent Claim
261 words
A dual port static random access memory, comprising: a first N-type MOS transistor, comprising a gate connecting to a first word line, a source/drain region connecting to a first bit line, and the other source/drain region connecting to a first node: a second N-type MOS transistor, comprising a gate connecting to the first word line, a source/drain region connecting to a second bit line, and the other source/drain region connecting to a second node; a third N-type MOS transistor, comprising a gate connecting to the second node, a source/drain region connecting to ground, and the other source/drain region connecting to the first node; fourth N-type MOS transistor, comprising a gate connecting to the first node, a source/drain region connecting to the ground, and the other source/drain region connecting to the second node, a first P-type MOS transistor, comprising a gate connecting to a second word line, a source/drain region connecting to a third bit line, and the other source/drain region connecting to the first node; a second P-type MOS transistor, comprising a gate connecting to the second word line, a source/drain region connecting to a fourth bit line, and the other source/drain region connecting to the second node; a third P-type MOS transistor, comprising a gate connecting to the second node, a source/drain region connectinig to a power source, and the other source/drain region connecting to the first node; and a fourth P-type MOS transistor, comprising a gate connecting to the first node, a source/drain region connecting to the power source, and the other source/drain region connecting to the second node.
Claim 7
Dependent Claim
49 words
The dual port static random access memory according to claim 4, comprising a pass gate which includes a same number of the N-type MOS transistors selected from the first to the fourth N-type MOS transistors and the P-type transistors selected from the first to the fourth P-type MOS transistors.
Claim 8
Dependent Claim
55 words
The dual port static random access memory according to claim 5, wherein two N-type MOS transistors are selected with two of the first to the fourth bit lines as first pass gates, and two P-type MOS transistors are selected with the other two of the first to the fourth bit lines as second pass gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |