US6025744A
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Glitch free delay line multiplexing technique
Assignee: GlobalFoundries Inc
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Filing: 1998-04-17
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Granted: 2000-02-15
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Expires: 2018-04-17
Abstract
Abstract A glitch free delay line multiplexing technique is described that includes an intermediate multiplexing system and an output multiplexer. The intermediate multiplexing system receives signals from a plurality of delay units and outputs a subset of delay signals that includes the signal presently selected, the signal presently selected with an additional delay, and the signal presently selected with one less delay. The intermediate multiplexing system receives a control word from a select mechanism in a non-time critical manner. The output multiplexer receives the least significant bits of the control word and outputs the selected signal.
Inventors
- 👤 Allan R. Bertolet
- 👤 Albert M. Chu
- 👤 Frank D. Ferraiolo
- 👤 Samuel K. Weinstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:33
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K5/125; H03K5/1252; H03K2005/00013; H03K2005/00019; H03K2005/00058; H03K2005/0015; H03K2005/00156
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
166 words
A glitch free delay line system comprising: a clock signal; a variable delay line comprising a plurality of sequentially coupled delay units, wherein the delay line comprises M output nodes and each of the M output nodes reproduces the clock signal with a varying amount of delay; a select mechanism for choosing a predetermined amount of delay n, and for generating a selection signal in response thereto; an M-to-N multiplexor having: M inputs for receiving each of the delayed clock signals from the M output nodes, a select input for receiving the selection signal from the select mechanism, and N output lines, wherein 3<N<M, and wherein three of the N output lines provide clock signals having delays of n, n-1, and n+1; and an N-to-1 multiplexor having: N inputs coupled to the N output lines of the M-to-N multiplexor, a select input for receiving the selection signal from the select mechanism, and an output line, wherein the output line outputs the clock signal with n delay.
Claim 2
Dependent Claim
166 words
A glitch free delay line system comprising: a clock signal; a variable delay line comprising a plurality of sequentially coupled delay units, wherein the delay line comprises M output nodes and each of the M output nodes reproduces the clock signal with a varying amount of delay; a select mechanism for choosing a predetermined amount of delay n, and for generating a selection signal in response thereto; an M-to-N multiplexor having: M inputs for receiving each of the delayed clock signals from the M output nodes, a select input for receiving the selection signal from the select mechanism, and N output lines, wherein 3<N<M, and wherein three of the N output lines provide clock signals having delays of n, n-1, and n+1; and an N-to-1 multiplexor having: N inputs coupled to the N output lines of the M-to-N multiplexor, a select input for receiving the selection signal from the select mechanism, and an output line, wherein the output line outputs the clock signal with n delay.
Claim 3
Dependent Claim
20 words
The system of claim 1 wherein the N output lines further provide a signal having a delay of "don't care."
Claim 4
Dependent Claim
15 words
The system of claim 1 wherein the select mechanism is synchronized with the clock signal.
Claim 5
Dependent Claim
9 words
The system of claim 1 wherein N equals four.
Claim 6
Dependent Claim
21 words
The system of claim 1 wherein the select input of the N-to-1 multiplexor receives only a portion of the selection signal.
Claim 7
Dependent Claim
39 words
The system of claim 1 wherein the M-to-N multiplexor includes combinatorial logic for choosing the appropriate M output nodes based on the selection signal in order to provide the three clock signals having delays of n, n-1, and n+1.
Claim 8
Dependent Claim
80 words
A glitchless delay line circuit, comprising: delay means for generating a plurality of delayed clock signals; selection means for selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n; filter means for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and output means for receiving the subset of delayed clock signals and for generating the clock signal having n delay.
Claim 9
Dependent Claim
80 words
A glitchless delay line circuit, comprising: delay means for generating a plurality of delayed clock signals; selection means for selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n; filter means for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and output means for receiving the subset of delayed clock signals and for generating the clock signal having n delay.
Claim 10
Dependent Claim
42 words
The circuit of claim 7 wherein the selection means comprises: means for delivering a first signal to the filter means; and means for delivering a second signal to the output means, wherein the second signal comprises a portion of the first signal.
Claim 11
Dependent Claim
20 words
The circuit of claim 8 wherein the second signal reaches the output means before the subset reaches the output means.
Claim 12
Dependent Claim
92 words
A delay lock loop comprising: a phase detection system; and a variable delay line, comprising: a plurality of delay units for generating a plurality of delayed clock signals, wherein each has a varying amount of delay; a selection mechanism for selecting the clock signal having n delay; a filter mechanism for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and an output mechanism for receiving the subset of delayed clock signals and for generating the clock signal having n delay.
Claim 13
Dependent Claim
92 words
A delay lock loop comprising: a phase detection system; and a variable delay line, comprising: a plurality of delay units for generating a plurality of delayed clock signals, wherein each has a varying amount of delay; a selection mechanism for selecting the clock signal having n delay; a filter mechanism for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and an output mechanism for receiving the subset of delayed clock signals and for generating the clock signal having n delay.
Claim 14
Dependent Claim
31 words
The delay lock loop of claim 10 wherein the selection mechanism delivers a control word to the filter mechanism and delivers a portion of the control word to the output mechanism.
Claim 15
Dependent Claim
25 words
The delay lock loop of claim 11 wherein the portion of the control word affects the output mechanism before the subset affects the output mechanism.
Claim 16
Dependent Claim
83 words
A delay line circuit, comprising: a delay system for generating a plurality of delayed clock signals; a selection system for selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n; a filter system for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and an output system for receiving the subset of delayed clock signals and for generating the clock signal having n delay.
Claim 17
Dependent Claim
83 words
A delay line circuit, comprising: a delay system for generating a plurality of delayed clock signals; a selection system for selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n; a filter system for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and an output system for receiving the subset of delayed clock signals and for generating the clock signal having n delay.
Claim 18
Dependent Claim
44 words
The circuit of claim 13 wherein the selection system comprises: a system for delivering a first signal to the filter system; and a system for delivering a second signal to the output means, wherein the second signal comprises a portion of the first signal.
Claim 19
Dependent Claim
20 words
The circuit of claim 14 wherein the second signal reaches the output system before the subset reaches the output system.
Claim 20
Independent Claim
75 words
A method for generating a glitch free delayed clock signal, comprising the steps of: generating a plurality of delayed clock signals; selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n; generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and receiving the subset of delayed clock signals and generating the clock signal having n delay.
Claim 21
Independent Claim
75 words
A method for generating a glitch free delayed clock signal, comprising the steps of: generating a plurality of delayed clock signals; selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n; generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and receiving the subset of delayed clock signals and generating the clock signal having n delay.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |