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US6025235A
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Short channel transistor having resistive gate extensions
Assignee: GlobalFoundries Inc
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Filing: 1998-03-10
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Granted: 2000-02-15
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Expires: 2018-03-10
Abstract
Abstract A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively. A method for making the transistor structure of the present invention is also provided. In one aspect, the invention comprises: forming a transistor region on a silicon substrate, the region including a first and second spacers on a first side and a second side of the region, respectively, the spacers overlying a first oxide layer on the surface of the substrate; etching the first oxide layer leaving a first and second gaps between the first and second spacers, respectively, and the silicon substrate; forming a gate oxide layer overlying the surface of the substrate in the transistor region, the gate oxide having a thickness; and filling the transistor region with polysilicon to cover the gate oxide region.
Inventors
- 👤 Zoran Krivokapic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:13
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D30/00; H10D30/01; H10D30/021; H10D30/0217; H10D30/0223; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/018; H10D64/021; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10D30/0212; H10D64/017; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
109 words
A method for forming a transistor comprising the sequential steps of: forming a transistor region on a silicon substrate, the region including a first and second control spacers on a first side and a second side of the region, respectively, the spacers overlying a first oxide layer on the surface of the substrate; etching the first oxide layer leaving a first and second gaps between the first and second spacers, respectively, and the silicon substrate; forming a gate oxide layer overlying the surface of the substrate in the transistor region, the gate oxide having a thickness; and filling the transistor region with polysilicon to cover the gate oxide region.
Claim 2
Independent Claim
109 words
A method for forming a transistor comprising the sequential steps of: forming a transistor region on a silicon substrate, the region including a first and second control spacers on a first side and a second side of the region, respectively, the spacers overlying a first oxide layer on the surface of the substrate; etching the first oxide layer leaving a first and second gaps between the first and second spacers, respectively, and the silicon substrate; forming a gate oxide layer overlying the surface of the substrate in the transistor region, the gate oxide having a thickness; and filling the transistor region with polysilicon to cover the gate oxide region.
Claim 3
Dependent Claim
84 words
The method of claim 1 wherein said step of forming a transistor region comprises the substeps of: (A) forming a pattern stack; (B) forming pattern spacers adjacent to the pattern stack; (C) forming a trench isolation about the pattern stack; and (D) removing the pattern spacers; (E) depositing an epitaxial layer over the trench oxide and adjacent to the pattern stack (F) removing the pattern stack; and (G) forming the control spacers in the region to control said short channel length of the device.
Claim 4
Dependent Claim
80 words
The method of claim 2 wherein said step (A) comprises the substeps of: sequentially depositing said first oxide layer, a first nitride layer, a second oxide layer and a second nitride layer on said substrate, each said layer having a layer length, a layer width and a layer height, said second nitride layer having a second nitride layer top surface; and etching said first and second oxide layers and said first and second nitride layers to form a pattern stack.
Claim 5
Dependent Claim
30 words
The method of claim 2 wherein said step (B) comprises the substeps of: (i) forming oxide spacers about the pattern stack; and (ii) forming nitride spacers about the nitride spacers.
Claim 6
Dependent Claim
64 words
The method of claim 2 wherein said step (C) comprises: forming an oxide trench into said substrate, said oxide trench extending above said substrate, said extension being along said first nitride spacer lateral surface; depositing a trench oxide into said oxide trench, said trench oxide having a trench oxide top surface; and polishing the trench oxide top surface and second nitride layer top surface.
Claim 7
Dependent Claim
28 words
The method of claim 1 further including the step of: forming a source and drain region by depositing an impurity into the epitaxial layer and heating the substrate.
Claim 8
Independent Claim
109 words
A method for forming a short channel transistor, comprising the steps of: forming a definition stack comprising an oxide layer, a first silicon nitride layer, a second, thick oxide layer, and a second silicon nitride layer; forming first spacers adjacent to the stack; forming isolation oxide about the stack and spacers; removing second silicon nitride layer, the second oxide layer and the first nitride layer, leaving a transistor formation region in the isolation oxide; forming a second nitride spacer in the transistor region; removing the first oxide layer; forming a gate oxide layer having at least a portion underlying the second spacers; and filling the transistor region with silicon.
Claim 9
Independent Claim
109 words
A method for forming a short channel transistor, comprising the steps of: forming a definition stack comprising an oxide layer, a first silicon nitride layer, a second, thick oxide layer, and a second silicon nitride layer; forming first spacers adjacent to the stack; forming isolation oxide about the stack and spacers; removing second silicon nitride layer, the second oxide layer and the first nitride layer, leaving a transistor formation region in the isolation oxide; forming a second nitride spacer in the transistor region; removing the first oxide layer; forming a gate oxide layer having at least a portion underlying the second spacers; and filling the transistor region with silicon.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |