Methods of forming field effect transistors and related field effect transistor constructions

Claim 1

A method of forming a field effect transistor comprising: forming a masking layer over a semiconductive substrate; forming an opening through the masking layer and defining a substrate area over which a field effect transistor gate is to be formed; providing a dopant of a first conductivity type through the opening and into the substrate; after providing the dopant through the opening, forming sidewall spacers over respective sidewalls of the opening; providing an enhancement dopant of a second conductivity type which is different from the first conductivity type through the opening and into the substrate; and forming a transistor gate within the opening proximate the sidewall spacers, and providing source/drain regions of the second conductivity type into the substrate and operably proximate the transistor gate, the providing of the dopant of the first conductivity type forming a halo region proximate the source/drain regions.

Claim 2

A method of forming a field effect transistor comprising: forming a masking layer over a semiconductive substrate; forming an opening through the masking layer and defining a substrate area over which a field effect transistor gate is to be formed; providing a dopant of a first conductivity type through the opening and into the substrate; after providing the dopant through the opening, forming sidewall spacers over respective sidewalls of the opening; providing an enhancement dopant of a second conductivity type which is different from the first conductivity type through the opening and into the substrate; and forming a transistor gate within the opening proximate the sidewall spacers, and providing source/drain regions of the second conductivity type into the substrate and operably proximate the transistor gate, the providing of the dopant of the first conductivity type forming a halo region proximate the source/drain regions.

Claim 12

A method of forming a PMOS field effect transistor comprising: providing a substrate having an active area defined between a pair of spaced-apart isolation regions; forming a masking layer over the substrate; forming an opening in masking layer and defining an area over which a field effect transistor is to be formed, the opening comprising a pair of sidewalls which face one another; conducting a first-energy implant of a first n-type dopant through the opening and into the substrate, the first-energy implant defining a first average elevational dopant level within the substrate; conducting a second-energy implant of a second n-type dopant through the opening and into the substrate, the second-energy implant defining a second average elevational dopant level within the substrate which is different from the first average elevational dopant level, the first and second energies being different; forming a sacrificial oxide layer over the substrate area within the opening; forming a layer comprising an insulative material over the substrate within the opening and over the sacrificial oxide layer; selectively etching the insulative material layer relative to the sacrificial oxide layer to form sidewall spacers over the opening's sidewalls; providing p-type dopant through an opening defined by the sidewall spacers and into the substrate; removing the sacrificial oxide layer; forming a gate oxide layer over the substrate between the sidewall spacers; forming a conductively-doped polysilicon transistor gate layer over the substrate and between the sidewall spacers; forming a silicide layer over the transistor gate layer; planarizing the transistor gate layer and the silicide layer relative to the masking layer and forming a transistor gate; removing the masking layer; providing p-type impurity into the substrate on either side of the transistor gate and defining source/drain diffusion regions of the transistor; and annealing the substrate sufficiently to form lightly doped drain regions operably proximate the transistor gate and halo regions operably proximate the respective source/drain diffusion regions.

Claim 13

A method of forming a PMOS field effect transistor comprising: providing a substrate having an active area defined between a pair of spaced-apart isolation regions; forming a masking layer over the substrate; forming an opening in masking layer and defining an area over which a field effect transistor is to be formed, the opening comprising a pair of sidewalls which face one another; conducting a first-energy implant of a first n-type dopant through the opening and into the substrate, the first-energy implant defining a first average elevational dopant level within the substrate; conducting a second-energy implant of a second n-type dopant through the opening and into the substrate, the second-energy implant defining a second average elevational dopant level within the substrate which is different from the first average elevational dopant level, the first and second energies being different; forming a sacrificial oxide layer over the substrate area within the opening; forming a layer comprising an insulative material over the substrate within the opening and over the sacrificial oxide layer; selectively etching the insulative material layer relative to the sacrificial oxide layer to form sidewall spacers over the opening's sidewalls; providing p-type dopant through an opening defined by the sidewall spacers and into the substrate; removing the sacrificial oxide layer; forming a gate oxide layer over the substrate between the sidewall spacers; forming a conductively-doped polysilicon transistor gate layer over the substrate and between the sidewall spacers; forming a silicide layer over the transistor gate layer; planarizing the transistor gate layer and the silicide layer relative to the masking layer and forming a transistor gate; removing the masking layer; providing p-type impurity into the substrate on either side of the transistor gate and defining source/drain diffusion regions of the transistor; and annealing the substrate sufficiently to form lightly doped drain regions operably proximate the transistor gate and halo regions operably proximate the respective source/drain diffusion regions.