Method and apparatus for detecting an input signal

Claim 2

A level detector fully integrated in an integrated circuit chip for detecting a level of an input signal, comprising: a rectifier operatively coupled to receive the input signal and provide a rectified signal; an anti-aliasing filter operatively coupled to the rectifier and comprising a first amplifier having a signal input operatively coupled to receive the rectified signal and having a signal output for providing a filtered signal, and a first DC offset canceling circuit that essentially eliminates all DC voltage offsets by auto-zeroing the anti-aliasing filter and storing a first voltage offset of the first amplifier during a first time period and providing the first voltage offset to cancel a second voltage offset produced by the first amplifier during a second time period, the DC offset canceling circuit comprising an offset eliminating switch operatively connected to the signal input of the first amplifier; a switched integrating capacitor coupled to the offset eliminating switch, the switched integrating capacitor coupled to the signal output of the first amplifier; an auto-zeroing switch operatively connected to the signal input of the first amplifier and the signal output of the first amplifier; and one or more pairs of a series capacitor and a series switch, wherein the series capacitor comprises a first terminal and a second terminal, the first terminal operatively connected to the offset eliminating switch and the signal input of the first amplifier, and wherein the series switch is operatively connected to the second terminal of the series capacitor and is operatively connected to receive the rectified signal from the rectifier; a decimator operatively coupled to the anti-aliasing filter to sample the filtered signal at a decimation sample rate and provide decimated samples of the filtered signal; and a low-pass filter operatively coupled to the decimator to receive the decimated samples of the filtered signal and to output a detected level.

Claim 3

A level detector according to claim 1, wherein the input signal comprises a voice signal and wherein the low-pass filter has a response time which tracks an amplitude of the voice signal.

Claim 4

A level detector according to claim 1, wherein the level detector is provided in a compandor.

Claim 5

A level detector according to claim 2, wherein the compandor includes a variable gain stage operatively coupled to apply a gain to the input signal based on the detected level from the low-pass filter.

Claim 6

A level detector according to claim 1, wherein the level detector is provided in a expandor.

Claim 7

A level detector according to claim 1, wherein the level detector is provided in a compressor.

Claim 8

A level detector according to claim 1, wherein the rectifier is a time-sampled full wave rectifier.

Claim 9

A level detector according to claim 1, wherein the anti-aliasing filter comprises a time-sampled anti-aliasing filter operatively coupled to the rectifier to provide the filtered signal in samples.

Claim 10

A level detector according to claim 1, wherein the anti-aliasing filter has a frequency response sufficient to attenuate high frequency components of the rectified signal at frequencies near integral multiples of the decimation sample rate.

Claim 11

A level detector according to claim 1, wherein the decimation sample rate of the decimator is chosen to minimize a total combined surface area of an integrated circuit implementation of the anti-aliasing filter and the low-pass filter.

Claim 12

A level detector according to claim 1, wherein the low-pass filter is a time-sampled low-pass filter.

Claim 13

A level detector according to claim 1, wherein the low-pass filter has a passband to pass the decimated samples of the filtered signal at frequencies below frequencies of the input signal.

Claim 14

A level detector according to claim 1, wherein the low-pass filter comprises: a second amplifier having a signal input operatively coupled to receive the decimated samples from the decimator and having a signal output; and a second DC offset canceling circuit that essentially eliminates all DC voltage offsets, comprising a second auto-zeroed offset-storage means operatively coupled to the second amplifier for auto-zeroing the low-pass filter and for storing a third voltage offset of the second amplifier during a third time period and for providing the third voltage offset to cancel a fourth voltage offset produced by the second amplifier during a fourth time period.

Claim 15

A level detector according to claim 13, wherein the second auto-zeroed offset-storage means comprises: an offset eliminating switch operatively connected to the signal input of the second amplifier; a switched integrating capacitor coupled to the offset eliminating switch, the switched integrating capacitor coupled to the signal output of the second amplifier; an auto-zeroing switch operatively connected to the switched integrating capacitor and to the offset eliminating switch; and one or more pairs of a series capacitor and a series switch, wherein the series capacitor comprises a first terminal and a second terminal, the first terminal operatively connected to the offset eliminating switch and the signal input of the second amplifier, and wherein the series switch is operatively connected to the second terminal of the series capacitor and is operatively connected to receive decimated samples from the decimator.

Claim 16

A level detector according to claim 14, wherein the input signal comprises a voice signal and wherein the switched integrating capacitor has a capacitance for the low-pass filter to have a response time which tracks an amplitude of the voice signal.

Claim 17

A level detector according to claim 13, wherein the level detector is provided in a compander and the compander comprises a variable gain stage operatively coupled to apply a gain to the input signal based on the detected level from the low-pass filter.

Claim 18

A level detector fully integrated in an integrated circuit chip for detecting a level of an input signal, comprising: a rectifier operatively coupled to receive the input signal and provide a rectified signal; an anti-aliasing filter operatively coupled to the rectifier, comprising a first amplifier having a signal input operatively coupled to receive the rectified signal from the rectifier and having a signal output for providing a filtered signal, and a first DC offset canceling circuit that essentially eliminates all DC voltage offsets, comprising a first offset eliminating switch operatively connected to the signal input of the first amplifier, a first switched integrating capacitor coupled to the first offset eliminating switch, the first switched integrating capacitor coupled to the signal output of the first amplifier, a first auto-zeroing switch operatively connected to the first switched integrating capacitor and to the first offset eliminating switch, and one or more pairs of a first series capacitor and a first series switch, wherein the first series capacitor comprises a first terminal and a second terminal, the first terminal operatively connected to the first offset eliminating switch and the signal input of the first amplifier, and wherein the first series switch is operatively connected to the second terminal of the first series capacitor and is operatively connected to receive the rectified signal from the rectifier; a decimator operatively coupled to the anti-aliasing filter to sample the filtered signal from the anti-aliasing filter at a decimation sample rate and provide decimated samples of the filtered signal; and a low-pass filter operatively coupled to the decimator to receive the decimated samples of the filtered signal and output a detected level, comprising a second amplifier having a signal input operatively coupled to receive decimated samples from the decimator and having a signal output, and a second DC offset canceling circuit that essentially eliminates all DC voltage offsets, comprising a second offset eliminating switch operatively connected to the signal input of the second amplifier; a second switched integrating capacitor coupled between the second offset eliminating switch, the second switched integrating capacitor coupled to the signal output of the second amplifier, a second auto-zeroing switch operatively connected to the second switched integrating capacitor and to the second offset eliminating switch, and one or more pairs of a second series capacitor and a second series switch, wherein the second series capacitor comprises a first terminal and a third terminal, the first terminal operatively connected to the second offset eliminating switch and the second signal input of the second amplifier, and wherein the second series switch is operatively connected to the second terminal of the second series capacitor and is operatively connected to receive decimated samples from the decimator.

Claim 19

A level detector fully integrated in an integrated circuit chip for detecting a level of an input signal, comprising: a rectifier operatively coupled to receive the input signal and provide a rectified signal; an anti-aliasing filter operatively coupled to the rectifier, comprising a first amplifier having a signal input operatively coupled to receive the rectified signal from the rectifier and having a signal output for providing a filtered signal, and a first DC offset canceling circuit that essentially eliminates all DC voltage offsets, comprising a first offset eliminating switch operatively connected to the signal input of the first amplifier, a first switched integrating capacitor coupled to the first offset eliminating switch, the first switched integrating capacitor coupled to the signal output of the first amplifier, a first auto-zeroing switch operatively connected to the first switched integrating capacitor and to the first offset eliminating switch, and one or more pairs of a first series capacitor and a first series switch, wherein the first series capacitor comprises a first terminal and a second terminal, the first terminal operatively connected to the first offset eliminating switch and the signal input of the first amplifier, and wherein the first series switch is operatively connected to the second terminal of the first series capacitor and is operatively connected to receive the rectified signal from the rectifier; a decimator operatively coupled to the anti-aliasing filter to sample the filtered signal from the anti-aliasing filter at a decimation sample rate and provide decimated samples of the filtered signal; and a low-pass filter operatively coupled to the decimator to receive the decimated samples of the filtered signal and output a detected level, comprising a second amplifier having a signal input operatively coupled to receive decimated samples from the decimator and having a signal output, and a second DC offset canceling circuit that essentially eliminates all DC voltage offsets, comprising a second offset eliminating switch operatively connected to the signal input of the second amplifier; a second switched integrating capacitor coupled between the second offset eliminating switch, the second switched integrating capacitor coupled to the signal output of the second amplifier, a second auto-zeroing switch operatively connected to the second switched integrating capacitor and to the second offset eliminating switch, and one or more pairs of a second series capacitor and a second series switch, wherein the second series capacitor comprises a first terminal and a third terminal, the first terminal operatively connected to the second offset eliminating switch and the second signal input of the second amplifier, and wherein the second series switch is operatively connected to the second terminal of the second series capacitor and is operatively connected to receive decimated samples from the decimator.

Claim 22

A method according to claim 18, wherein the step (b) of anti-aliasing filtering filters the input signal in discrete time samples to provide the filtered signal in samples.

Claim 23

A method according to claim 18, wherein the step (b) of anti-alias filtering filters the rectified signal with a frequency response sufficient to attenuate high frequency components of the rectified signal at frequencies near integral multiples of the decimation sample rate.

Claim 24

A method according to claim 18, wherein the step (e) of low-pass filtering filters with a passband to pass the decimated signals at frequencies below frequencies of the input signal.

Claim 25

A method according to claim 18, wherein the input signal comprises a voice signal and wherein the step (e) of low-pass filtering filters with a response time which tracks an amplitude of the voice signal.

Claim 26

A method according to claim 18, further comprising the step of (f) companding by variably applying a gain to the input signal in accordance with the detected level provided by the low-pass filtering of the step (e).

Claim 27

A method according to claim 18, further comprising the step of (f) eliminating essentially all DC offsets introduced in step (e) by auto-zeroing the low-pass filtering and by storing a third voltage offset during a third time period and using the third voltage offset to cancel a fourth voltage offset during a fourth time period.