Patent US3437978A successfully refreshed from Google Patents.
US6022792A
Expired / Lapsed
US
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Semiconductor dicing and assembling method
Assignee: Ablic Inc
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Filing: 1997-03-12
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Granted: 2000-02-08
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Expires: 2017-03-12
Abstract
Abstract To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
Inventors
- 👤 Kazutoshi Ishii
- 👤 Naoto Inoue
- 👤 Koushi Maemura
- 👤 Shoji Nakanishi
- 👤 Yoshikazu Kojima
- 👤 Kiyoaki Kadoi
- 👤 Takao Akiba
- 👤 Yasuhiro Moya
- 👤 Kentaro Kuhara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:08
CPC Classifications
H; H10; H10P; H10P54/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4421; H10W72/00; H10W72/01; H10W72/019; H10W72/20; H10W70/00; H10W70/60; H10W72/071; H10W72/0711; H10W72/07141; H10W72/075; H10W72/07531; H10W72/07532; H10W72/07551; H10W72/07553; H10W72/231; H10W72/234; H10W72/241; H10W72/244; H10W72/251; H10W72/252; H10W72/29; H10W72/50; H10W72/531; H10W72/536; H10W72/59; H10W72/90; H10W72/921; H10W72/923; H10W72/931; H10W72/932; H10W72/934; H10W72/936; H10W72/941; H10W72/9415; H10W72/951; H10W72/952; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
101 words
A method of manufacturing a semiconductor integrated circuit, comprising the steps of: forming a plurality of transistors on a surface of a semiconductor region of a silicon wafer, metal-interconnecting electrodes of said transistors; forming a protecting film on said metal interconnection; first cutting said wafer along a scribed region of said wafer deeper than a depth of a diffusion layer of impurities; and second cutting said wafer along the scribed region of said wafer which was cut during the first cutting, characterized in that a cutting speed in said first cutting step is less than that in said second cutting step.
Claim 2
Independent Claim
101 words
A method of manufacturing a semiconductor integrated circuit, comprising the steps of: forming a plurality of transistors on a surface of a semiconductor region of a silicon wafer, metal-interconnecting electrodes of said transistors; forming a protecting film on said metal interconnection; first cutting said wafer along a scribed region of said wafer deeper than a depth of a diffusion layer of impurities; and second cutting said wafer along the scribed region of said wafer which was cut during the first cutting, characterized in that a cutting speed in said first cutting step is less than that in said second cutting step.
Claim 3
Dependent Claim
23 words
The method of claim 1, wherein said first cutting step is an etching process and the second cutting step is a mechanical process.
Claim 4
Dependent Claim
23 words
The method of claim 1, wherein said first cutting step is a mechanical process and the second cutting step is a mechanical process.
Claim 5
Independent Claim
36 words
The method of claims 1, wherein if the diffusion layer is a source-drain region of a transistor, the scribed region is being cut during the first cutting step at the depth of at least 2 microns.
Claim 6
Dependent Claim
36 words
The method of claim 1, wherein if the diffusion layer is a well of a CMOS transistor, the scribed region is being cut during the first cutting step at the depth of at least 5 microns.
Claim 7
Dependent Claim
26 words
The method of claim 1, wherein the scribed region is being cut during the first cutting step at the depth of about 2 to 50 microns.
Claim 8
Dependent Claim
27 words
The method of claim 1, wherein the width of the scribed region formed during the first cutting step is wider than that of the second cutting step.
Claim 9
Dependent Claim
36 words
The method of claim 2, wherein if the diffusion layer is a source-drain region of a transistor, the scribed region is being cut during the first cutting step at the depth of at least 2 microns.
Claim 10
Dependent Claim
36 words
The method of claim 2, wherein if the diffusion layer is a well of a CMOS transistor, the scribed region is being cut during the first cutting step at the depth of at least 5 microns.
Claim 11
Dependent Claim
26 words
The method of claim 2, wherein the scribed region is being cut during the first cutting step at the depth of about 2 to 50 microns.
Claim 12
Dependent Claim
27 words
The method of claim 2, wherein the width of the scribed region formed during the first cutting step is wider than that of the second cutting step.
Claim 13
Independent Claim
172 words
A method of manufacturing a semiconductor integrated circuit, comprising the steps of: forming an integrated circuit on a surface of a semiconductor wafer; forming a protecting film on a surface of said integrated circuit; perforating said protecting film at an area on drain region to form a pad portion as an external connecting terminal region; forming a solder bump electrode on said pad portion; scribing said semiconductor wafer into a chip; spraying a resin flux cored solder on a surface of said solder bump electrode located on a surface of said chip; adhering said chip to said printed circuit board to be implemented, in a face down manner, at a predetermined location and aligning said chip to said printed circuit board using a through hole of the printed circuit board at which said solder bump electrode and a metal interconnection of said printed circuit board are superposed to each other; and heating said chip from a rear surface of said chip and forming a shielding film on a surface of said chip.
Claim 14
Independent Claim
172 words
A method of manufacturing a semiconductor integrated circuit, comprising the steps of: forming an integrated circuit on a surface of a semiconductor wafer; forming a protecting film on a surface of said integrated circuit; perforating said protecting film at an area on drain region to form a pad portion as an external connecting terminal region; forming a solder bump electrode on said pad portion; scribing said semiconductor wafer into a chip; spraying a resin flux cored solder on a surface of said solder bump electrode located on a surface of said chip; adhering said chip to said printed circuit board to be implemented, in a face down manner, at a predetermined location and aligning said chip to said printed circuit board using a through hole of the printed circuit board at which said solder bump electrode and a metal interconnection of said printed circuit board are superposed to each other; and heating said chip from a rear surface of said chip and forming a shielding film on a surface of said chip.
Claim 15
Dependent Claim
22 words
The method of claim 12, wherein the printed circuit board has perforated portions to align the chip with the printed circuit board.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-07 | 2003-08-09 | 2004-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-07 | 2007-08-09 | 2008-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-07 | 2011-08-09 | 2012-02-08 | $7700.00 | Window Closed / Lapsed |