US4073055A
Expired / Lapsed
US
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Method for manufacturing semiconductor devices
Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1977-02-22
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Granted: 1978-02-14
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Expires: 1997-02-22
Abstract
Abstract A method for the manufacture of semiconductor devices comprises the steps of forming a number of mutually electrically isolated semiconductor islands on an insulating substrate and cutting a semiconductor wafer, made of semiconductor elements and substrate, along its dicing line to provide a number of semiconductor chips, the method characterized in that additional semiconductor islands are formed on the insulating substrate simultaneously with, or after, the formation of the first-mentioned semi-conductor islands so that each substantially surrounds the chip. The method permits very easy mask alignments for photoengraving as well as a clear judgment as to whether or not the formation of contact openings has been completed.
Inventors
- 👤 Minoru Kimura
- 👤 Hiroyuki Tango
- 👤 Yukio Ohmori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:34
CPC Classifications
H; H10; H10P; H10P52/00; H10P34/00; H10P34/40; H10P34/42; H10P54/00; H10W; H10W46/00; H10W46/501
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
96 words
A method for manufacturing semiconductor devices, comprising the steps of a. selectively forming first and second semiconductor regions on an insulating substrate, said first semiconductor region constituting a semiconductor element in a later step and said second semiconductor region being formed in a manner to substantially surround a semiconductor chip which is cut away from a semiconductor wafer along its dicing line in a later step; b. forming said semiconductor element on said first semiconductor region; and c. cutting said semiconductor chip away from said semiconductor wafer along the dicing line marked on said second region.
Claim 2
Independent Claim
96 words
A method for manufacturing semiconductor devices, comprising the steps of a. selectively forming first and second semiconductor regions on an insulating substrate, said first semiconductor region constituting a semiconductor element in a later step and said second semiconductor region being formed in a manner to substantially surround a semiconductor chip which is cut away from a semiconductor wafer along its dicing line in a later step; b. forming said semiconductor element on said first semiconductor region; and c. cutting said semiconductor chip away from said semiconductor wafer along the dicing line marked on said second region.
Claim 3
Dependent Claim
35 words
The method according to claim 1, in which after a semiconductor layer is formed on an insulating substrate said first and second regions are formed by selectively removing the semiconductor layer on the insulating substrate.
Claim 4
Dependent Claim
29 words
The method according to claim 1, in which after said first semiconductor region is formed on the substrate, said second region is formed on the substrate in another step.
Claim 5
Dependent Claim
37 words
The method according to claim 1, in which a silicon layer formed on the insulating substrate is selectively oxidized to provide an isolating region through which said first and second regions are formed on the insulating substrate.
Claim 6
Dependent Claim
68 words
The method according to claim 1, in which, when contact openings for the semiconductor element is formed by etching, an insulating layer on the surface of said second semiconductor region is removed by said etching to expose the surface of said second semiconductor region, the exposed surface of said second semiconductor region being utilized to judge whether or not the formation of said contact openings has been completed.
Claim 7
Dependent Claim
19 words
The method according to claim 1, in which said second semiconductor region is continuously formed around the semiconductor chip.
Claim 8
Dependent Claim
19 words
The method according to claim 1, in which said second semiconductor region is intermittently formed around the semiconductor chip.
Claim 9
Dependent Claim
29 words
The method according to claim 1, in which said first semiconductor region is formed of one kind selected from the group consisting of single crystal silicon and polycrystalline silicon.
Claim 10
Dependent Claim
29 words
The method according to claim 1, in which said second semiconductor region is formed of one kind selected from the group consisting of single crystal silicon and polycrystalline silicon.
Claim 11
Dependent Claim
15 words
The method according to claim 1, in which said insulating substrate is a sapphire substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-13 | 1981-08-15 | 1982-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-13 | 1985-08-15 | 1986-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-13 | 1989-08-15 | 1990-02-14 | $7700.00 | Window Closed / Lapsed |