US6022776A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of using silicon oxynitride to improve fabricating of DRAM contacts and landing pads
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-04-07
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Granted: 2000-02-08
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Expires: 2019-04-07
Abstract
Abstract A method for forming a DRAM cell of a DRAM circuit is disclosed. The DRAM circuit includes a periphery region and a cell region. The DRAM cell is in the cell region and comprises an access transistor and a capacitor. The access transistor has a gate, a source, and a drain. The periphery region includes a plurality of gates. The method comprises the deposition of a silicon oxynitride layer over the gates, the silicon oxynitride layer acting as a bottom anti-reflection coating. That portion of the silicon oxynitride layer that lies over the DRAM cell is removed. A landing pad is formed over the source of the access transistor and a bitline pad is formed over the drain of the transistor. Next, a first oxide layer is formed over the landing pad and the bitline pad. A capacitor is formed over the landing pad and a second oxide layer is formed over the capacitor. Finally, metal contacts are formed to at least one of the gates in the periphery region using the silicon oxynitride layer as a buffer layer to prevent substrate loss or overetching.
Inventors
- 👤 Wan Yih Lien
- 👤 Kung Linliu
- 👤 Meng-Jaw Cherng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:52
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
174 words
A method for forming a DRAM cell of a DRAM circuit, said DRAM circuit including a periphery region and a cell region, said DRAM cell being in said cell region and comprised of an access transistor and a capacitor, said access transistor having a gate, a source, and a drain, said periphery region including a plurality of gates, the method comprising the steps of: depositing a silicon oxynitride layer over said gates, said silicon oxynitride layer acting as a bottom anti-reflection coating and directly in contact with said gates; removing said silicon oxynitride layer that lies over said DRAM cell; forming a landing pad over said source and a bitline pad over said drain; forming a first oxide layer over said landing pad and said bitline pad; forming a capacitor over said landing pad; forming a second oxide layer over said capacitor; and forming metal contacts to at least on of said plurality of gates in said periphery region using said silicon oxynitride layer as a buffer layer to prevent substrate loss or overetching.
Claim 2
Independent Claim
174 words
A method for forming a DRAM cell of a DRAM circuit, said DRAM circuit including a periphery region and a cell region, said DRAM cell being in said cell region and comprised of an access transistor and a capacitor, said access transistor having a gate, a source, and a drain, said periphery region including a plurality of gates, the method comprising the steps of: depositing a silicon oxynitride layer over said gates, said silicon oxynitride layer acting as a bottom anti-reflection coating and directly in contact with said gates; removing said silicon oxynitride layer that lies over said DRAM cell; forming a landing pad over said source and a bitline pad over said drain; forming a first oxide layer over said landing pad and said bitline pad; forming a capacitor over said landing pad; forming a second oxide layer over said capacitor; and forming metal contacts to at least on of said plurality of gates in said periphery region using said silicon oxynitride layer as a buffer layer to prevent substrate loss or overetching.
Claim 3
Dependent Claim
18 words
The method of claim 1 further including planarizing said second oxide layer prior to forming said metal contacts.
Claim 4
Independent Claim
110 words
A method of forming a capacitor node for a DRAM cell, the method comprising: depositing a polysilicon layer on a substrate; depositing a tungsten silicide layer on said polysilicon layer; depositing a silicon oxynitride layer directly over and in contact with said tungsten silicide layer; patterning and etching said polysilicon layer, said tungsten silicide layer and said silicon oxynitride layer to form a gate stack; forming silicon nitride sidewall spacers on said gate stack; forming an oxide layer over said gate stack; forming at least one polysilicon plug in said oxide layer adjacent to said gate stack; and forming a bottom storage node for said capacitor atop said polysilicon plug.
Claim 5
Independent Claim
110 words
A method of forming a capacitor node for a DRAM cell, the method comprising: depositing a polysilicon layer on a substrate; depositing a tungsten silicide layer on said polysilicon layer; depositing a silicon oxynitride layer directly over and in contact with said tungsten silicide layer; patterning and etching said polysilicon layer, said tungsten silicide layer and said silicon oxynitride layer to form a gate stack; forming silicon nitride sidewall spacers on said gate stack; forming an oxide layer over said gate stack; forming at least one polysilicon plug in said oxide layer adjacent to said gate stack; and forming a bottom storage node for said capacitor atop said polysilicon plug.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-07 | 2003-08-09 | 2004-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-07 | 2007-08-09 | 2008-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-07 | 2011-08-09 | 2012-02-08 | $7700.00 | Window Closed / Lapsed |