Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
148 words
A method for forming a contact to a semiconductor element adjacent to a gate electrode comprising: (a) providing a silicon wafer having a conductive gate electrode with a superjacent insulative cap layer and a subjacent gate insulative layer, said gate electrode also having an insulative sidewall structure and an active semiconductor element within the surface of said silicon wafer adjacent to said sidewall structure; (b) depositing a silicon enriched silicon oxynitride layer over said silicon wafer; (c) depositing an insulative layer over said silicon enriched silicon oxynitride layer; (d) depositing a photoresist layer over said insulative layer; (e) patterning said photoresist layer to define a contact opening; (f) etching said insulative layer with a unidirectional etching technique, thereby exposing said silicon enriched silicon oxynitride layer; (g) etching said silicon enriched silicon oxynitride layer thereby forming said contact opening; and (h) depositing a conductive material into said contact opening.
Claim 2
Independent Claim
148 words
A method for forming a contact to a semiconductor element adjacent to a gate electrode comprising: (a) providing a silicon wafer having a conductive gate electrode with a superjacent insulative cap layer and a subjacent gate insulative layer, said gate electrode also having an insulative sidewall structure and an active semiconductor element within the surface of said silicon wafer adjacent to said sidewall structure; (b) depositing a silicon enriched silicon oxynitride layer over said silicon wafer; (c) depositing an insulative layer over said silicon enriched silicon oxynitride layer; (d) depositing a photoresist layer over said insulative layer; (e) patterning said photoresist layer to define a contact opening; (f) etching said insulative layer with a unidirectional etching technique, thereby exposing said silicon enriched silicon oxynitride layer; (g) etching said silicon enriched silicon oxynitride layer thereby forming said contact opening; and (h) depositing a conductive material into said contact opening.
Claim 3
Dependent Claim
82 words
The method of claim 1 wherein said silicon enriched silicon oxynitride layer is deposited by PECVD at a temperature of between about 320° C. and 380° C. and pressure of between about 3,000 and 8,000 mTorr, using precursors SiH 4 at a flow rate of between about 80 and 90 SCCM and N 2 O at a flow rate of between about 80 and 100 SCCM in a helium carrier gas at a flow rate of between about 2,000 and 2,500 SCCM.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said silicon enriched silicon oxynitride layer is between about 200 and 1,000 Angstroms thick.
Claim 5
Dependent Claim
20 words
The method of claim 1 wherein said silicon enriched silicon oxynitride layer contains a silicon oxide portion in its base.
Claim 6
Dependent Claim
25 words
The method of claim 1 wherein said insulative layer is selected from the group consisting of silicon oxide, a phosphosilicate glass, and a borophosphosilicate glass.
Claim 7
Dependent Claim
24 words
The method of claim 1 wherein said unidirectional etching technique is reactive-ion-etching using an etchant containing CF 4 , CHF 3 , and Argon.
Claim 8
Dependent Claim
18 words
The method of claim 1 wherein said silicon enriched silicon oxinitride layer is etched by reactive ion etching.
Claim 9
Independent Claim
171 words
A method for forming a contact to a semiconductor element adjacent to a gate electrode comprising: (a) providing a silicon wafer having a gate insulative layer subjacent to a doped polysilicon layer; (b) depositing a first silicon enriched silicon oxynitride layer over said silicon wafer; (c) depositing and patterning a first photoresist layer to define a gate electrode; (d) anisotropically etching said first silicon enriched silicon oxynitride layer and said doped polysilicon layer; (e) implanting a first dose of impurity atoms; (f) depositing a second silicon enriched silicon oxynitride layer; (g) anisotropically etching said second silicon enriched silicon oxynitride layer thereby forming sidewalls; (h) implanting a second dose of impurity atoms thereby forming a semiconductor element; (i) depositing an insulative layer over said silicon wafer; (j) depositing a second photoresist layer over said insulative layer; (k) patterning said second photoresist layer to define a contact opening; (l) etching said insulative layer with a unidirectional etching technique, thereby forming said contact opening; and (m) depositing a conductive material into said contact opening.
Claim 10
Independent Claim
171 words
A method for forming a contact to a semiconductor element adjacent to a gate electrode comprising: (a) providing a silicon wafer having a gate insulative layer subjacent to a doped polysilicon layer; (b) depositing a first silicon enriched silicon oxynitride layer over said silicon wafer; (c) depositing and patterning a first photoresist layer to define a gate electrode; (d) anisotropically etching said first silicon enriched silicon oxynitride layer and said doped polysilicon layer; (e) implanting a first dose of impurity atoms; (f) depositing a second silicon enriched silicon oxynitride layer; (g) anisotropically etching said second silicon enriched silicon oxynitride layer thereby forming sidewalls; (h) implanting a second dose of impurity atoms thereby forming a semiconductor element; (i) depositing an insulative layer over said silicon wafer; (j) depositing a second photoresist layer over said insulative layer; (k) patterning said second photoresist layer to define a contact opening; (l) etching said insulative layer with a unidirectional etching technique, thereby forming said contact opening; and (m) depositing a conductive material into said contact opening.
Claim 11
Dependent Claim
86 words
The method of claim 8 wherein said first and said second silicon enriched silicon oxynitride layers are deposited by PECVD at a temperature of between about 320° C. and 380° C. and pressure of between about 3,000 and 8,000 mTorr, using precursors SiH 4 at a flow rate of between about 80 and 90 SCCM and N 2 O at a flow rate of between about 80 and 100 SCCM in a helium carrier gas at a flow rate of between about 2,000 and 2,500 SCCM.
Claim 12
Dependent Claim
21 words
The method of claim 8 wherein said first silicon enriched silicon oxynitride layer is between about 200 and 1,000 Angstroms thick.
Claim 13
Dependent Claim
24 words
The method of claim 8 wherein said first and said second silicon enriched silicon oxynitride layers contain a silicon oxide portion in their base.
Claim 14
Dependent Claim
20 words
The method of claim 8 wherein said first and said second silicon enriched silicon oxynitride layers are etched by reactive-ion-etching.
Claim 15
Dependent Claim
25 words
The method of claim 8 wherein said insulative layer is selected from the group consisting of silicon oxide, a phosphosilicate glass, and a borophosphosilicate glass.
Claim 16
Dependent Claim
12 words
The method of claim 8 wherein said anisotropic etching technique is reactive-ion-etching.
Claim 17
Independent Claim
115 words
A method of protecting a stacked gate edge on a semiconductor device to minimize erosion and damage of elements of said stacked gate edge during field oxide etching of a self-aligned-source (SAS) region comprising: (a) providing a silicon wafer having a stacked gate edge positioned over alternating regions of field oxide and silicon active area; (b) depositing a conformal silicon enriched silicon oxynitride layer over said silicon wafer; (c) depositing and patterning a photoresist mask to expose a SAS region; (c) etching said regions of field oxide in said SAS region; and (d) performing a source implant whereby, during etching, the silicon enriched silicon oxynitride layer protects the edges of the stacked gate from erosion.
Claim 18
Independent Claim
115 words
A method of protecting a stacked gate edge on a semiconductor device to minimize erosion and damage of elements of said stacked gate edge during field oxide etching of a self-aligned-source (SAS) region comprising: (a) providing a silicon wafer having a stacked gate edge positioned over alternating regions of field oxide and silicon active area; (b) depositing a conformal silicon enriched silicon oxynitride layer over said silicon wafer; (c) depositing and patterning a photoresist mask to expose a SAS region; (c) etching said regions of field oxide in said SAS region; and (d) performing a source implant whereby, during etching, the silicon enriched silicon oxynitride layer protects the edges of the stacked gate from erosion.
Claim 19
Dependent Claim
83 words
The method of claim 15 wherein said conformal silicon enriched silicon oxynitride layer is deposited by PECVD at a temperature of between about 320° C. and 380° C. and pressure of between about 3,000 and 8,000 mTorr, using precursors SiH 4 at a flow rate of between about 80 and 90 SCCM and N 2 O at a flow rate of between about 80 and 100 SCCM in a helium carrier gas at a flow rate of between about 2,000 and 2,500 SCCM.
Claim 20
Dependent Claim
20 words
The method of claim 15 wherein said silicon enriched silicon oxynitride layer is between about 200 and 1,000 Angstroms thick.
Claim 21
Dependent Claim
20 words
The method of claim 15 wherein said silicon enriched silicon oxynitride layer contains a silicon oxide portion in its base.