US6021469A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardware virtual machine instruction processor
Assignee: Oracle America Inc
•
Filing: 1997-01-23
•
Granted: 2000-02-01
•
Expires: 2017-01-23
Abstract
Abstract A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.
Inventors
- 👤 Marc Tremblay
- 👤 James Michael O'Connor
- 👤 William N. Joy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 05:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30021; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0875; G06F9/30098; G06F9/3012; G06F9/30134; G06F9/3017; G06F9/30174; G06F9/30181; G06F9/34; G06F9/345; G06F9/38; G06F9/3877; G06F9/3879; G06F9/44; G06F9/445; G06F9/44589; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4488; G06F9/449; G06F9/455; G06F9/45504; G06F2212/00; G06F2212/45; G06F2212/451; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
131 words
A hardware virtual machine instruction processor comprising: a virtual machine instruction cache unit including: an instruction cache; and an instruction buffer coupled to said virtual machine instruction cache to receive a virtual machine instruction; a virtual machine instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said virtual machine instruction decode unit wherein said integer unit executes integer instructions; and a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache.
Claim 2
Dependent Claim
131 words
A hardware virtual machine instruction processor comprising: a virtual machine instruction cache unit including: an instruction cache; and an instruction buffer coupled to said virtual machine instruction cache to receive a virtual machine instruction; a virtual machine instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said virtual machine instruction decode unit wherein said integer unit executes integer instructions; and a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache.
Claim 3
Dependent Claim
19 words
A hardware virtual machine instruction processor as in claim 1 wherein said stack cache includes a local variables area.
Claim 4
Dependent Claim
18 words
A hardware virtual machine instruction processor as in claim 2 wherein said stack cache includes an operand stack.
Claim 5
Dependent Claim
22 words
A hardware virtual machine instruction processor as in claim 1 further comprising: a data cache unit coupled to said dribble management unit.
Claim 6
Dependent Claim
137 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a method argument cache coupled to an instruction decoder in said instruction decode unit.
Claim 7
Dependent Claim
137 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a method argument cache coupled to an instruction decoder in said instruction decode unit.
Claim 8
Dependent Claim
133 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache, and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a local variable look-aside cache in said stack management unit.
Claim 9
Dependent Claim
133 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache, and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a local variable look-aside cache in said stack management unit.
Claim 10
Dependent Claim
132 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a getfield-putfield acceleration unit coupled to said integer unit.
Claim 11
Dependent Claim
132 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a getfield-putfield acceleration unit coupled to said integer unit.
Claim 12
Dependent Claim
132 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a lookup-switch acceleration unit coupled to said integer unit.
Claim 13
Dependent Claim
132 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a lookup-switch acceleration unit coupled to said integer unit.
Claim 14
Dependent Claim
132 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a bounds check unit coupled to said integer unit.
Claim 15
Dependent Claim
132 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a bounds check unit coupled to said integer unit.
Claim 16
Dependent Claim
138 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a memory allocation accelerator in a data cache unit coupled to said dribble management unit.
Claim 17
Dependent Claim
138 words
A hardware virtual machine instruction processor comprising: an instruction cache unit including: an instruction cache; and an instruction buffer coupled to said instruction cache to receive a virtual machine instruction; an instruction decode unit coupled to said instruction buffer to receive said virtual machine instruction wherein said instruction decode unit generates a decoded virtual machine instruction; an integer unit coupled to said instruction decode unit wherein said integer unit executes integer instructions; a stack management unit coupled to said integer unit and to said virtual machine instruction decode unit, wherein said stack management unit further comprises: a stack cache; and a dribble management unit coupled to said stack cache wherein said dribble management unit fills and spills data from said stack cache; and a memory allocation accelerator in a data cache unit coupled to said dribble management unit.
References Cited (Backward Citations)
US3735363A
Cited
US3889243A
Cited
US4530049A
Cited
US5043870A
Cited
US4811208A
Cited
US4951194A
Cited
US5107457A
Cited
US5448707A
Cited
US5604877A
Cited
US5765035A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-31 | 2003-08-02 | 2004-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-31 | 2007-08-02 | 2008-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-31 | 2011-08-02 | 2012-02-01 | $7700.00 | Window Closed / Lapsed |