Arrangement for storing an information signal in a memory and for retrieving the information signal from said memory

Claim 1

An arrangement for intermediate storage of a video signal, said arrangement comprising: input means for receiving sequential video signal elements at a first average speed; first-in-first-out input bridging buffer memory means having an input fed by said input means, said input bridging buffer memory means having random access functionality for receiving said video signal elements and having an output interface; mass memory disc means having cross-track random access functionality for effecting said intermediate storage, and having write head means fed by said output interface of said input bridging buffer memory means and furthermore read head means; first-in-first-out output bridging buffer memory means having random access functionality and having an input interface fed by said read head means; and output means having an input fed by said read head means for outputting said sequential video signal elements at a second average speed, wherein said input bridging buffer memory means and said output bridging buffer memory means are exchangeably and coexistingly mapped on a single bridging buffer, for, through said random access functionality and said cross-track random access functionality, effecting an arbitrarily selectable intermediate storage delay with a maximum value corresponding to a storage capacity of said mass memory disc means and a granularity of the delay that is orders of magnitude lower than said maximum value, the storage capacity of said single bridging buffer corresponding to a fraction of the storage capacity of said mass memory disc means, wherein the storage capacity of said mass memory disc means allows a delay of the sequential video signal elements in said mass memory disc means in the order of several minutes or more, a granularity of the delay in said mass memory disc means being less than the storage capacity of the single bridging buffer, while the storage capacity of said single bridging buffer allows a delay of the sequential video signal elements in said single bridging buffer of, at most, a few seconds, whereby the arrangement allows simultaneous inputting and outputting of the sequential video signal elements, each at an average speed that corresponds to a standard receiving or displaying speed, respectively.