Phase locked delay circuit

Claim 2

A phase locked delay circuit for generating an internal clock signal synchronized with an external system clock signal, the circuit comprising: a delay buffer for receiving the external system clock signal, delaying the external system clock for a predetermined first delay time, and outputting the delayed clock signal as a first clock signal; a main delay unit coupled to said delay buffer for providing the first clock signal a main delay unit output node responsive to a flag signal being in a first state and for generating a second clock signal by delaying the first clock signal for a predetermined second delay time and providing the second clock signal to the main delay unit output node responsive to the flag signal being in a second state; a delay line coupled to said main delay unit including a plurality of serially connected unit delays for generating a plurality of sequentially delayed clock signals by receiving either the first or the second clock signal from said main delay unit and sequentially delaying the received signal for a predetermined unit time; means for detecting phase synchronization by comparing a phase of each of the sequentially delayed clock signals with a phase of the first clock signal responsive to the flag signal, generating a corresponding plurality of enable and carry signals, and activating an enable signal and a carry signal corresponding to one of the sequentially delayed clock signals in substantial phase with the first clock signal; a flag signal generator for generating the flag signal responsive to the plurality of carry signals and a reset signal; a switching unit coupled to said delay line including a plurality of switches for selecting one of the sequentially delayed signals responsive to the active enable signal; and a clock driver for receiving the signal selected by said switching unit, generating the internal clock signal by delaying the received signal for a predetermined third delay time.

Claim 3

The phase locked delay circuit of claim 1 wherein said main delay unit comprises: a main delay for delaying the first clock signal for the predetermined second delay time and providing the second clock signal to the main delay unit output node; a bypass path for bypassing said main delay and providing the first clock signal to the main delay unit output node; and main delay switching means for selecting either the main delay or the bypass path responsive to the flag signal.

Claim 4

The phase locked delay circuit of claim 2 wherein said main delay switching means comprises: a first switching device connected between said delay buffer and said main delay for providing the first clock signal to said main delay responsive to the flag signal; a second switching device connected between said main delay and said delay line for providing the second clock signal to the main delay unit output node responsive to the flag signal; a third switching device connected between said delay buffer and said bypass path for providing the first clock signal to said bypass path responsive to the flag signal; and a fourth switching device connected between said bypass path and said delay line for providing the first clock signal to the main delay unit output node responsive to the flag signal, said first and second switching devices being disabled when said third and fourth switching devices are enabled and said first and second switching devices being enabled when said third and fourth switching devices are disabled.

Claim 5

The phase locked delay circuit of claim 3 wherein said first, second, third, and fourth switching devices are transmission gates.

Claim 6

The phase locked delay circuit of claim 1 wherein each of the plurality of enable signals does not change states when the flag is in the first state.

Claim 7

The phase locked delay circuit of claim 1 wherein a phase difference between the first and second clock signals is equal to an external system clock period minus the first and second predetermined delay times.

Claim 8

The phase locked delay circuit of claim 1 wherein said flag signal generator generates the flag signal in the first state when the reset signal is in the first state and one of the carry signals is in the second state.

Claim 9

The phase locked delay circuit of claim 1 further comprising a reset signal generator for generating the reset signal, the reset signal being disabled once the internal clock is synchronized with the external system clock.

Claim 10

The phase locked delay circuit of claim 1 wherein the means for detecting phase synchronization includes a plurality of phase detectors, each of said plurality of phase detectors comprising: a phase comparator for receiving a corresponding sequentially delayed clock signal, comparing the phase of the received sequentially delayed clock signal with the phase of the first clock signal, and generating a phase synchronization signal, the phase synchronization signal being enabled when the phase of the sequentially delayed clock signal is the same as the phase of the first clock signal responsive to the flag signal; and a carry/enable signal generator for generating a carry and an enable signal responsive to the phase synchronization signal.

Claim 11

The phase locked delay circuit of claim 9 wherein said phase comparator maintains a state of the phase synchronization signal when the flag signal is in the first state.

Claim 12

The phase locked delay circuit of claim 9 wherein said phase comparator comprises: first switching means for transmitting the received sequentially delayed clock signal to a first switching means output node responsive to the flag and first clock signal; a first latch coupled to said first switching means for generating a first latched signal by latching the signal transmitted to the first switching means output node; an inverter coupled to said first latch for inverting the first latched signal; second switching means coupled to said inverter for transmitting the inverted first latched signal to a second switching means output node responsive to the first clock signal; and a second latch coupled to said second switching means for generating the phase synchronization signal by latching the signal transmitted to the second switching means output node.

Claim 13

The phase locked delay circuit of claim 1 wherein said means for detecting phase synchronization comprises: operation selecting means for selecting an operation according to user need; and a selective phase comparison detector for generating a first enable signal responsive to the selected operation of said operation selecting means.

Claim 18

The method of claim 14 wherein selecting the delayed second clock signal includes enabling at least one of a plurality of switches connected between the plurality of unit delays and a third clock signal line.

Claim 19

The method of claim 14 further including generating a flag signal responsive to a reset signal.

Claim 20

The method of claim 16 wherein generating the first clock signal is responsive to the flag signal and generating the second clock signal is responsive to the flag signal.

Claim 21

The method of claim 16 wherein generating a second clock signal includes applying the first clock signal to a main delay unit when the flag signal is in a first state to thereby delay the first clock signal by the second predetermined delay time and produce a second clock signal at a main delay unit output node.

Claim 22

The method of claim 18 wherein generating a first clock signal includes bypassing the main delay unit and providing the first clock signal to the main delay unit output node when the flag signal is in a second state.

Claim 23

The method of claim 19 further including generating a plurality of carry and enable signals responsive to the first clock signal and the flag signal.

Claim 26

The method of claim 21 wherein generating a second clock signal includes applying the first clock signal to a main delay unit when the flag signal is in the first state to thereby delay the first clock signal by the second predetermined delay time and produce a second clock signal at a main delay unit output node.

Claim 27

The method of claim 22 wherein generating a first clock signal includes bypassing the main delay unit and providing the first clock signal to the main delay unit output node when the flag signal is in a second state.

Claim 28

The method of claim 23 further including generating a plurality of carry and enable signals responsive to the first clock signal and the flag signal.

Claim 31

A phase locked delay circuit or generating an internal clock signal synchronized with an external system clock signal, the circuit comprising: a delay buffer for receiving the external system clock signal, delaying the external system clock for a predetermined first delay time, and outputting the delayed clock signal as a first clock signal; a main delay unit coupled to said delay buffer for providing the first clock signal to a main delay unit output node using a bypass path when a flag signal is in a high logic state and for generating a second clock signal by delaying the first clock signal for a predetermined second delay time by applying the first clock signal to a main delay and providing the second clock signal to the main delay unit output node responsive to the flag signal being in a low logic state; a delay line coupled to said main delay unit including a plurality of serially connected unit delays for generating a plurality of sequentially delayed clock signals by receiving either the first or the second clock signal from said main delay unit and sequentially delaying the received signal for a predetermined unit time; phase synchronization detector coupled to said delay line including a plurality of phase comparison detectors for comparing a phase of each of the sequentially delayed clock signals with a phase of the first clock signal responsive to the flag signal, selecting one of the sequentially delayed clock signals having a phase substantially the same as a phase of the first clock signal, generating a corresponding plurality of enable and carry signals, and activating an enable signal of said plurality of enable signals and a carry signal of said plurality of carry signals corresponding to the selected sequentially delayed clock signal, wherein states of the plurality of enable signals are maintained when the flag is in the high logic state; a flag signal generator for generating the flag signal responsive to the plurality of carry signals and a reset signal; a switching unit coupled to said delay line including a plurality of switches for selecting one of the sequentially delayed signals responsive to the active enable signal; and a clock driver for receiving the signal selected by said switching unit, generating the internal clock signal by delaying the received signal for a predetermined third delay time, wherein the predetermined third delay time is equal to the sum of the first and second delay times.

Claim 32

A phase locked delay circuit or generating an internal clock signal synchronized with an external system clock signal, the circuit comprising: a delay buffer for receiving the external system clock signal, delaying the external system clock for a predetermined first delay time, and outputting the delayed clock signal as a first clock signal; a main delay unit coupled to said delay buffer for providing the first clock signal to a main delay unit output node using a bypass path when a flag signal is in a high logic state and for generating a second clock signal by delaying the first clock signal for a predetermined second delay time by applying the first clock signal to a main delay and providing the second clock signal to the main delay unit output node responsive to the flag signal being in a low logic state; a delay line coupled to said main delay unit including a plurality of serially connected unit delays for generating a plurality of sequentially delayed clock signals by receiving either the first or the second clock signal from said main delay unit and sequentially delaying the received signal for a predetermined unit time; phase synchronization detector coupled to said delay line including a plurality of phase comparison detectors for comparing a phase of each of the sequentially delayed clock signals with a phase of the first clock signal responsive to the flag signal, selecting one of the sequentially delayed clock signals having a phase substantially the same as a phase of the first clock signal, generating a corresponding plurality of enable and carry signals, and activating an enable signal of said plurality of enable signals and a carry signal of said plurality of carry signals corresponding to the selected sequentially delayed clock signal, wherein states of the plurality of enable signals are maintained when the flag is in the high logic state; a flag signal generator for generating the flag signal responsive to the plurality of carry signals and a reset signal; a switching unit coupled to said delay line including a plurality of switches for selecting one of the sequentially delayed signals responsive to the active enable signal; and a clock driver for receiving the signal selected by said switching unit, generating the internal clock signal by delaying the received signal for a predetermined third delay time, wherein the predetermined third delay time is equal to the sum of the first and second delay times.