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US6015725A
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Vertical field effect transistor and manufacturing method thereof
Assignee: Sony Corp
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Filing: 1997-08-19
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Granted: 2000-01-18
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Expires: 2017-08-19
Abstract
Abstract A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).
Inventors
- 👤 Teruo Hirayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/025; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00; H10D30/0411; H10D30/60; H10D30/63; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/016; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
175 words
A method of manufacturing a vertical field effect transistor, comprising in the following order the steps of: forming separate buried layers of a second conduction type by ion implantation to a predetermined depth in a semiconductor substrate of a first conduction type; forming a recess for each buried layer, each recess having a width smaller than the width of said buried layer and having the bottom thereof located within said buried layer of said semiconductor substrate and with adjacent recesses being separated by a protrusion; forming a gate insulation film on the side walls of the protrusion; forming a gate electrode on the gate insulating film on the side wall of the protrusion; forming an impurity region making up a source and a drain on the surface of said protrusion and on the bottom surface of said recess; providing an insulating layer to cover the protrusions and fill the recesses; forming an opening in the insulating layer above each protrusion; and forming a plug contact in the opening contacting the upper surface of each protrusion.
Claim 2
Independent Claim
175 words
A method of manufacturing a vertical field effect transistor, comprising in the following order the steps of: forming separate buried layers of a second conduction type by ion implantation to a predetermined depth in a semiconductor substrate of a first conduction type; forming a recess for each buried layer, each recess having a width smaller than the width of said buried layer and having the bottom thereof located within said buried layer of said semiconductor substrate and with adjacent recesses being separated by a protrusion; forming a gate insulation film on the side walls of the protrusion; forming a gate electrode on the gate insulating film on the side wall of the protrusion; forming an impurity region making up a source and a drain on the surface of said protrusion and on the bottom surface of said recess; providing an insulating layer to cover the protrusions and fill the recesses; forming an opening in the insulating layer above each protrusion; and forming a plug contact in the opening contacting the upper surface of each protrusion.
Claim 3
Dependent Claim
23 words
A method of manufacturing a vertical field effect transistor according to claim 1, wherein said buried layer is thermally diffused after ion implantation.
Claim 4
Dependent Claim
118 words
A method according to claim 1, wherein the step of forming separate buried layers includes forming an insulating film layer on the semiconductor material before ion implantation and then forming a first mask on the insulating film layer for the ion implantation, and wherein the step of forming a recess includes etching portions of the insulating film layer using the first mask to form remaining portions, then removing the first mask, covering the remaining portions of the insulating film layer with an insulating oxide film, etching the insulating oxide film to form side wall films on the remaining portions and then using the remaining portions with the side wall films as a second mask when forming the recesses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-17 | 2003-07-19 | 2004-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-17 | 2007-07-19 | 2008-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-17 | 2011-07-19 | 2012-01-18 | $7700.00 | Window Closed / Lapsed |