Patent US6014442A successfully refreshed from Google Patents.
US6014442A
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US
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Decrypting method and electronic device
Assignee: Sony Corp
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Filing: 1997-01-30
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Granted: 2000-01-11
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Expires: 2017-01-30
Abstract
Abstract PID information and TSC information are extracted from a header of received data inputted to a terminal 1 and are supplied to an IDT (16). The IDT (16) receives these information and searches a data key from a DPMEM (17) by an indirect retrieving method and reads the data key. Plural data keys updated every predetermined period are non-synchronously written to the DPMEM (17). This writing operation is inhibited when the writing and reading operations of the DPMEM (17) are performed in the same timing and the same address. Thus, memory control of the DPMEM (17) can be easily performed. Accordingly, all decryption processings can be completed in real time on a reception side.
Inventors
- 👤 Masahiko Enari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:58
CPC Classifications
H; H04; H04L; H04L9/00; H04L9/08; H04L9/06; H04L9/0618; H04L9/0637; H04L9/0861; H04L9/0891; H04L2209/00; H04L2209/24
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
140 words
A decrypting method comprising the steps of: writing plural key information to memory means; reading any one of the key information designated by information in k-bit input data from said memory means, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n, such that said m+n-bit key address is shorter than said k-bit input data; decrypting said input data on the basis of key information read in the reading step; and inhibiting the writing step when executing periods of said writing step and said reading step overlap each other and write and read addresses are in conformity with each other.
Claim 2
Dependent Claim
140 words
A decrypting method comprising the steps of: writing plural key information to memory means; reading any one of the key information designated by information in k-bit input data from said memory means, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n, such that said m+n-bit key address is shorter than said k-bit input data; decrypting said input data on the basis of key information read in the reading step; and inhibiting the writing step when executing periods of said writing step and said reading step overlap each other and write and read addresses are in conformity with each other.
Claim 3
Dependent Claim
17 words
An electronic device comprising at least decrypting means for executing the decrypting method claimed in claim 1.
Claim 4
Dependent Claim
131 words
A decrypting method comprising the steps of: reading any one of key information from memory means storing plural key information on the basis of k-bit input data, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n such that said key address is shorter than said k-bit input data; and decrypting said input data on the basis of the key information read in the reading step; said reading step being set such that a least key address is selected when two or more key addresses are assigned the same key information.
Claim 5
Dependent Claim
131 words
A decrypting method comprising the steps of: reading any one of key information from memory means storing plural key information on the basis of k-bit input data, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n such that said key address is shorter than said k-bit input data; and decrypting said input data on the basis of the key information read in the reading step; said reading step being set such that a least key address is selected when two or more key addresses are assigned the same key information.
Claim 6
Dependent Claim
17 words
An electronic device comprising at least decrypting means for executing the decrypting method claimed in claim 3.
Claim 7
Dependent Claim
131 words
A decrypting method comprising the steps of: reading any one of key information from memory means storing plural key information on the basis of k-bit input data, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n, such that said m+n-bit key address is shorter than said k-bit input data; and decrypting said input data on the basis of the key information read in the reading step; said reading step being set such that no key information is read when there is no key address corresponding to the k-bit input data.
Claim 8
Dependent Claim
131 words
A decrypting method comprising the steps of: reading any one of key information from memory means storing plural key information on the basis of k-bit input data, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n, such that said m+n-bit key address is shorter than said k-bit input data; and decrypting said input data on the basis of the key information read in the reading step; said reading step being set such that no key information is read when there is no key address corresponding to the k-bit input data.
Claim 9
Dependent Claim
17 words
An electronic device comprising at least decrypting means for executing the decrypting method claimed in claim 5.
Claim 10
Dependent Claim
137 words
A decrypting method comprising the steps of: performing an initializing operation; writing plural key information to memory means; reading any one of the key information from said memory means on the basis of k-bit input data, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n, such that said m+n-bit key address is shorter than said k-bit input data; and decrypting said input data on the basis of the key information read in the reading step; with the processing being performed in the initializing step being such that no key addresses are generated within an initializing period.
Claim 11
Dependent Claim
137 words
A decrypting method comprising the steps of: performing an initializing operation; writing plural key information to memory means; reading any one of the key information from said memory means on the basis of k-bit input data, the read key information being read from a key address that is generated by encoding said k-bit input data to form m-bit data and concatenating said m-bit data with n-bit data, wherein k, m and n are integers greater than or equal to one and k is greater than m+n, such that said m+n-bit key address is shorter than said k-bit input data; and decrypting said input data on the basis of the key information read in the reading step; with the processing being performed in the initializing step being such that no key addresses are generated within an initializing period.
Claim 12
Dependent Claim
17 words
An electronic device comprising at least decrypting means for executing the decrypting method claimed in claim 7.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |