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Patent US6009531A successfully refreshed from Google Patents.
US6009531A
Expired / Lapsed
US
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Transition analysis and circuit resynthesis method and device for digital circuit modeling
Assignee: Mentor Graphics Corp
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Filing: 1997-05-27
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Granted: 1999-12-28
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Expires: 2017-05-27
Abstract
Abstract A method of configuring a configurable logic system, including a single or multi-FPGA network, is disclosed in which an internal clock signal is defined that has a higher frequency than timing signals the system receives from the environment in which it is operating. The frequency can be at least ten times higher than a frequency of the environmental timing signals. The logic system is configured to have a controller that coordinates operation of its logic operation in response to the internal clock signal and environmental timing signals. Specifically, the controller is a finite state machine that provides control signals to sequential logic elements such as flip-flops. The logic elements are clocked by the internal clock signal. In the past, emulation or simulation devices, for example, operated in response to timing signals from the environment. A new internal clock signal, invisible to the environment, rather than the timing signals is used to control the internal operations of the devices. Additionally, a specific set of transformations are disclosed that enable the conversion of a digital circuit design with an arbitrary clocking methodology into a single clock synchronous circuit.
Inventors
- 👤 Charles W. Selvidge
- 👤 Matthew L. Dahl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:36
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F1/00; G06F1/04; G06F1/10; G06F30/34
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
99 words
A method of configuring a configurable logic system to operate in an environment, the logic system generating output signals to the environment in response to at least one environmental timing signal and environmental data signals provided from the environment, the method comprising: configuring the logic system to perform logic operations for generating the output signals in response to the environmental data signals and an internal clock signal; and configuring the logic system to comprise a finite state machine for generating control signals to control the logic operations in response to the environmental timing signal and the internal clock signal.
Claim 2
Independent Claim
99 words
A method of configuring a configurable logic system to operate in an environment, the logic system generating output signals to the environment in response to at least one environmental timing signal and environmental data signals provided from the environment, the method comprising: configuring the logic system to perform logic operations for generating the output signals in response to the environmental data signals and an internal clock signal; and configuring the logic system to comprise a finite state machine for generating control signals to control the logic operations in response to the environmental timing signal and the internal clock signal.
Claim 3
Dependent Claim
32 words
A method of configuring as described in claim 1, further comprising configuring the logic system to comprise a synchronizer for sampling the environmental timing signal in response to the internal clock signal.
Claim 4
Dependent Claim
21 words
A method of configuring as described in claim 1, wherein the logic system comprises at least one field programmable gate array.
Claim 5
Dependent Claim
27 words
A method of configuring as described in claim 1, further comprising configuring the finite stare machine to dictate set-up and hold times of signals to the environment.
Claim 6
Dependent Claim
25 words
A method of configuring as described in claim 1, further comprising configuring the finite state machine to dictate sampling times of the environmental data signals.
Claim 7
Dependent Claim
27 words
A method of configuring as described in claim 1, further comprising configuring the logic system to have combinational logic and sequential logic to perform the logic operations.
Claim 8
Dependent Claim
36 words
A method of configuring as described in claim 6, further comprising configuring the finite state machine to generate control signals to the sequential logic in response to the environmental timing signal and the internal clock signal.
Claim 9
Dependent Claim
36 words
A method of configuring as described in claim 7, further comprising configuring the sequential logic to comprise flip-flops receiving the internal clock signal at a clock input and the control signals at a latch enable input.
Claim 10
Dependent Claim
31 words
A method of configuring as described in claim 1, wherein the logic system comprises a plurality of configurable logic devices electrically connected via an interconnect for transmitting signals between the chips.
Claim 11
Dependent Claim
16 words
A method of configuring as described in claim 9, wherein the interconnect comprises cross bar chips.
Claim 12
Dependent Claim
16 words
A method as configuring as described in claim 9, wherein the interconnect utilizes a direct-connect topology.
Claim 13
Dependent Claim
14 words
A method of configuring as described in claim 11, wherein the interconnect includes buses.
Claim 14
Dependent Claim
92 words
A logic system for generating output signals to an environment in response to at least one environmental timing signal and environmental data signals provided from the environment, the logic system comprising: an internal clock for generating an internal clock signal for the logic system; at least one configurable logic device including: logic which generates the output signals in response to the environmental data signals and the internal clock signal; and a finite state machine which coordinates operation of the logic in response to the internal clock signal and the environmental timing signal.
Claim 15
Dependent Claim
92 words
A logic system for generating output signals to an environment in response to at least one environmental timing signal and environmental data signals provided from the environment, the logic system comprising: an internal clock for generating an internal clock signal for the logic system; at least one configurable logic device including: logic which generates the output signals in response to the environmental data signals and the internal clock signal; and a finite state machine which coordinates operation of the logic in response to the internal clock signal and the environmental timing signal.
Claim 16
Dependent Claim
24 words
A logic system as described in claim 13, wherein the at least one configurable logic device comprises at least one field programmable gate array.
Claim 17
Dependent Claim
20 words
A logic system as described in claim 13, further comprising an interconnect for transmitting signals between plural configurable logic devices.
Claim 18
Dependent Claim
25 words
A logic system as described in claim 13, further comprising a synchronizer for sampling the environmental timing signal in response to the internal clock signal.
Claim 19
Dependent Claim
16 words
A logic system as described in claim 16, wherein the synchronizer is constructed from non-programmable logic.
Claim 20
Dependent Claim
17 words
A logic system as described in claim 13, wherein the logic comprises combinational logic and sequential logic.
Claim 21
Dependent Claim
32 words
A logic system as described in claim 18, wherein the sequential logic comprises flip-flops receiving the internal clock signal at a clock input and the control signals at a latch enable input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |