Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance

Claim 1

A method for fabricating damascene bit line structures, for peripheral and cell array regions, of a semiconductor chip, comprising the steps of: providing a first region of a semiconductor substrate, to be used as a peripheral region, of said semiconductor chip; providing a second region of said semiconductor substrate, to be used as a cell array region, of said semiconductor chip; forming a first set of transfer gate transistors, comprised of gate structures on gate insulator layers, and source and drain regions, in said peripheral region, of said semiconductor chip; forming a second set of transfer gate transistors, comprised of gate structures on gate insulator layers, and source and drain regions, in said cell array region, of said semiconductor chip; forming polysilicon contact plug structures, in a contact hole in a first insulator layer, in said cell array region, contacting underlying, said source and drain region, of said second set of transfer gate transistors; forming capacitor structures on a first set of said polysilicon contact plug structures; depositing a second insulator layer; forming a first damascene opening in said second insulator layer, and in said first insulator layer, in said peripheral region, of said DRAM chip, with said first damascene opening comprised of two parts, a top part comprised of a wide, deep trench opening, in said second insulator layer, and a bottom part, comprised of a narrow opening in said second insulator layer, and in said first insulator layer, exposing said source and drain region, of said first set of transfer gate transistors; forming a second damascene opening in said second insulator layer, in said cell array region of said DRAM chip, with said second damascene opening comprised of two parts, a top part comprised of a wide, shallow trench opening, in said second insulator layer, and a bottom part, comprised of a narrow opening in said second insulator layer, exposing the top surface of a second set of said polysilicon contact plug structures; forming a first bit line structure, in said first damascene opening, comprised of a thick metal shape, in said wide, deep trench opening, and a bottom part, comprised of a metal plug, in said narrow opening, contacting said source and drain region, of said first set of transfer gate transistors; and forming a second bit line structure, in said second damascene opening, comprised of a thin metal shape, in said wide, shallow opening, and a bottom part, comprised of a metal plug, in said narrow opening, contacting the top surface of said second set of said polysilicon contact plug structures.

Claim 2

A method for fabricating damascene bit line structures, for peripheral and cell array regions, of a semiconductor chip, comprising the steps of: providing a first region of a semiconductor substrate, to be used as a peripheral region, of said semiconductor chip; providing a second region of said semiconductor substrate, to be used as a cell array region, of said semiconductor chip; forming a first set of transfer gate transistors, comprised of gate structures on gate insulator layers, and source and drain regions, in said peripheral region, of said semiconductor chip; forming a second set of transfer gate transistors, comprised of gate structures on gate insulator layers, and source and drain regions, in said cell array region, of said semiconductor chip; forming polysilicon contact plug structures, in a contact hole in a first insulator layer, in said cell array region, contacting underlying, said source and drain region, of said second set of transfer gate transistors; forming capacitor structures on a first set of said polysilicon contact plug structures; depositing a second insulator layer; forming a first damascene opening in said second insulator layer, and in said first insulator layer, in said peripheral region, of said DRAM chip, with said first damascene opening comprised of two parts, a top part comprised of a wide, deep trench opening, in said second insulator layer, and a bottom part, comprised of a narrow opening in said second insulator layer, and in said first insulator layer, exposing said source and drain region, of said first set of transfer gate transistors; forming a second damascene opening in said second insulator layer, in said cell array region of said DRAM chip, with said second damascene opening comprised of two parts, a top part comprised of a wide, shallow trench opening, in said second insulator layer, and a bottom part, comprised of a narrow opening in said second insulator layer, exposing the top surface of a second set of said polysilicon contact plug structures; forming a first bit line structure, in said first damascene opening, comprised of a thick metal shape, in said wide, deep trench opening, and a bottom part, comprised of a metal plug, in said narrow opening, contacting said source and drain region, of said first set of transfer gate transistors; and forming a second bit line structure, in said second damascene opening, comprised of a thin metal shape, in said wide, shallow opening, and a bottom part, comprised of a metal plug, in said narrow opening, contacting the top surface of said second set of said polysilicon contact plug structures.

Claim 11

A method for fabricating a DRAM chip, on a semiconductor substrate, featuring low resistance bit line structures, in a peripheral region of said DRAM chip, and featuring bit line structures with low bit line to bit line coupling capacitance, in a cell array region of said DRAM chip, comprising the steps of: providing a first region of said semiconductor substrate, to be used for said peripheral region of said DRAM chip; providing a second region of said semiconductor substrate, to be used for said cell array region of said DRAM chip; forming a first set of transfer gate transistors, in said peripheral region of said DRAM chip, comprised of polycide gate structures on silicon dioxide gate layers, and source and drain regions; forming a second set of transfer gate transistors, in said cell array region of said DRAM chip, comprised of polycide gate structures on silicon dioxide gate insulator layers, and source and drain regions; depositing a first insulator layer; planarizing said first insulator layer; opening contact holes in said first insulator layer, exposing source and drain regions of said second set of transfer gate transistors, in said cell array region, of said DRAM chip; depositing a polysilicon layer; patterning of said polysilicon layer to form polysilicon contact plug structures, in said contact holes; forming stacked capacitor structures on a first set of said polysilicon contact plug structures; depositing a second insulator layer; planarizing said second insulator layer; forming a wide, deep trench opening in a top portion of said second insulator layer, in said peripheral region of said DRAM chip; forming a wide, shallow opening in top portion of said second insulator layer, in said cell array region of said DRAM chip; forming a narrow opening in bottom portion of said second insulator layer, and in said first insulator layer, resulting in a first damascene opening, comprised of a wide, deep trench shape, and an underlying, narrow shape, exposing a source and drain region of said first set of transfer gate transistors, in said peripheral region of said DRAM chip; forming a narrow opening in said bottom portion of said second insulator layer, resulting in a second damascene opening, comprised of a wide, shallow shape, and an underlying, narrow shape, in said second insulator layer, exposing a second set of polysilicon contact plug structures, in said cell array region of said DRAM chip; depositing a metal layer; removing said metal layer from the top surface of said second insulator layer, in said peripheral region of said DRAM chip, resulting in said low resistance bit line structure, in said first damascene opening, comprised of a thick metal shape, in said wide, deep trench opening, overlying a narrow metal plug, in said narrow opening, contacting said source and drain region, in said first set of transfer gate transistors chip; and removing said metal layer from the top surface of said second insulator layer, in said cell array region of said DRAM chip, resulting in bit line structures in said second damascene opening, with low bit line to bit line coupling capacitance, comprised of a thin metal shape, in said wide, shallow trench opening, overlying a metal plug, in said narrow opening, and contacting the top surface of said second set of said polysilicon contact plug structures.

Claim 12

A method for fabricating a DRAM chip, on a semiconductor substrate, featuring low resistance bit line structures, in a peripheral region of said DRAM chip, and featuring bit line structures with low bit line to bit line coupling capacitance, in a cell array region of said DRAM chip, comprising the steps of: providing a first region of said semiconductor substrate, to be used for said peripheral region of said DRAM chip; providing a second region of said semiconductor substrate, to be used for said cell array region of said DRAM chip; forming a first set of transfer gate transistors, in said peripheral region of said DRAM chip, comprised of polycide gate structures on silicon dioxide gate layers, and source and drain regions; forming a second set of transfer gate transistors, in said cell array region of said DRAM chip, comprised of polycide gate structures on silicon dioxide gate insulator layers, and source and drain regions; depositing a first insulator layer; planarizing said first insulator layer; opening contact holes in said first insulator layer, exposing source and drain regions of said second set of transfer gate transistors, in said cell array region, of said DRAM chip; depositing a polysilicon layer; patterning of said polysilicon layer to form polysilicon contact plug structures, in said contact holes; forming stacked capacitor structures on a first set of said polysilicon contact plug structures; depositing a second insulator layer; planarizing said second insulator layer; forming a wide, deep trench opening in a top portion of said second insulator layer, in said peripheral region of said DRAM chip; forming a wide, shallow opening in top portion of said second insulator layer, in said cell array region of said DRAM chip; forming a narrow opening in bottom portion of said second insulator layer, and in said first insulator layer, resulting in a first damascene opening, comprised of a wide, deep trench shape, and an underlying, narrow shape, exposing a source and drain region of said first set of transfer gate transistors, in said peripheral region of said DRAM chip; forming a narrow opening in said bottom portion of said second insulator layer, resulting in a second damascene opening, comprised of a wide, shallow shape, and an underlying, narrow shape, in said second insulator layer, exposing a second set of polysilicon contact plug structures, in said cell array region of said DRAM chip; depositing a metal layer; removing said metal layer from the top surface of said second insulator layer, in said peripheral region of said DRAM chip, resulting in said low resistance bit line structure, in said first damascene opening, comprised of a thick metal shape, in said wide, deep trench opening, overlying a narrow metal plug, in said narrow opening, contacting said source and drain region, in said first set of transfer gate transistors chip; and removing said metal layer from the top surface of said second insulator layer, in said cell array region of said DRAM chip, resulting in bit line structures in said second damascene opening, with low bit line to bit line coupling capacitance, comprised of a thin metal shape, in said wide, shallow trench opening, overlying a metal plug, in said narrow opening, and contacting the top surface of said second set of said polysilicon contact plug structures.