US6006343A
Expired / Lapsed
US
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Method and apparatus for streamlined testing of electrical circuits
Assignee: Texas Instruments Inc
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Filing: 1997-06-27
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Granted: 1999-12-21
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Expires: 2017-06-27
Abstract
Abstract A serial scan test architecture permits complete scan test of a target circuit without requiring the test controller to interrupt its scan operation.
Inventors
- 👤 Lee D. Whetsel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:11
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31705; G01R31/31712; G01R31/31715; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318555
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
320 words
A system comprising: A. an address bus of signals; B. a data bus of signals; C. a control bus of signals; D. at least one peripheral circuit device connected to the address bus of signals, the data bus of signals and the control bus of signals, the at least one peripheral circuit device receiving address signals and control signals and reading and writing data signals on the bus of data signals in response to the address signals and control signals; and E. test circuits including: i. a test data input, a test data output, a test clock input, a test mode select input, a data input shift register and a data output shift register connected in series between the test data input and test data output, and a boundary input/output serializer connected to the data input register, the data output register, the test clock input and the test mode select input; ii. the test circuits being connected to the address bus of circuits, the data bus of circuits and the control bus of circuits, the address bus of signals coupling to the data input shift register, the data bus of signals coupling to the data input shift register and the data output shift register and the control bus of signals coupling to the boundary input/output serializer; iii. the data input shift register providing address signals, the data input shift register and the data output shift register respectively sending receiving data signals and the boundary input/output serializing providing control signals iv. the test circuits further including a test access ports receiving the test clock input and the test mode select input and producing a data register control output, the test circuits further including an instruction register receiving the data register control output and the boundary input/output serializer receiving the data register control output and carrying the data register control output to the data input shift register and the data output register.
Claim 2
Independent Claim
320 words
A system comprising: A. an address bus of signals; B. a data bus of signals; C. a control bus of signals; D. at least one peripheral circuit device connected to the address bus of signals, the data bus of signals and the control bus of signals, the at least one peripheral circuit device receiving address signals and control signals and reading and writing data signals on the bus of data signals in response to the address signals and control signals; and E. test circuits including: i. a test data input, a test data output, a test clock input, a test mode select input, a data input shift register and a data output shift register connected in series between the test data input and test data output, and a boundary input/output serializer connected to the data input register, the data output register, the test clock input and the test mode select input; ii. the test circuits being connected to the address bus of circuits, the data bus of circuits and the control bus of circuits, the address bus of signals coupling to the data input shift register, the data bus of signals coupling to the data input shift register and the data output shift register and the control bus of signals coupling to the boundary input/output serializer; iii. the data input shift register providing address signals, the data input shift register and the data output shift register respectively sending receiving data signals and the boundary input/output serializing providing control signals iv. the test circuits further including a test access ports receiving the test clock input and the test mode select input and producing a data register control output, the test circuits further including an instruction register receiving the data register control output and the boundary input/output serializer receiving the data register control output and carrying the data register control output to the data input shift register and the data output register.
Claim 3
Dependent Claim
14 words
The system of claim 1 including a data processor that includes the test circuits.
Claim 4
Dependent Claim
10 words
The system of claim 1 including plural peripheral circuit devices.
Claim 5
Dependent Claim
20 words
The system of claim 1 in which the boundary input/output serializer includes a programmable I/O controller providing the control signals.
Claim 6
Dependent Claim
148 words
A test device comprising: A. a test access port receiving a test clock input and a test mode input and producing first control signals; B. an instruction register receiving a test data input and the first control signals and producing a first test data output and second control signals; C. a boundary input/output serializer receiving the test data input and the first and second control signals and producing third control signals and a second test data output; D. plural data registers each receiving the test data input and the second and third control signals and producing third test data outputs; E. a first multiplexer receiving the second and third test data outputs and the second control signals and producing a fourth test data output; and F. a second multiplexer receiving the first and fourth test data outputs and the first control signals and producing a test data output.
Claim 7
Dependent Claim
148 words
A test device comprising: A. a test access port receiving a test clock input and a test mode input and producing first control signals; B. an instruction register receiving a test data input and the first control signals and producing a first test data output and second control signals; C. a boundary input/output serializer receiving the test data input and the first and second control signals and producing third control signals and a second test data output; D. plural data registers each receiving the test data input and the second and third control signals and producing third test data outputs; E. a first multiplexer receiving the second and third test data outputs and the second control signals and producing a fourth test data output; and F. a second multiplexer receiving the first and fourth test data outputs and the first control signals and producing a test data output.
Claim 8
Dependent Claim
15 words
The device of claim 5 in which the boundary input/output serializer is a state machine.
Claim 9
Dependent Claim
29 words
The device of claim 5 in which the boundary input/output serializer is a state machine that includes programmable circuitry for executing program instructions received from the test data input.
Claim 10
Dependent Claim
14 words
The device of claim 5 in which the boundary input/output serializer includes plural counters.
Claim 11
Dependent Claim
26 words
The device of claim 5 in which the boundary input/output serializer includes plural counters and respective count registers connected in series from the test data input.
Claim 12
Dependent Claim
17 words
The device of claim 5 in which there is one boundary input/output serializer for each data register.
Claim 13
Dependent Claim
165 words
An integrated circuit comprising: A. at least one data register; B. a boundary input/output serializer having a control output connected to the at least one data register, the boundary input/output serializer including programmable circuits, the boundary input/output serializer including a programmable I/O controller selectively connected to the control output of the boundary input/output serializer; C. an instruction register having an output connected to the at least one data register and the boundary input/output serializer; D. a test access port having an output connected to the boundary input/output serializer and the instruction register; E. a test clock pin connected to the test access port; F. a test mode select pin connected to the test access port; G. a test data input pin connected to the instruction register, the boundary input/output serializer and the at least one data register; and H. a test data output pin selectively connected to the test access port, the instruction register, the boundary input/output serializer and the at least one data register.
Claim 14
Dependent Claim
165 words
An integrated circuit comprising: A. at least one data register; B. a boundary input/output serializer having a control output connected to the at least one data register, the boundary input/output serializer including programmable circuits, the boundary input/output serializer including a programmable I/O controller selectively connected to the control output of the boundary input/output serializer; C. an instruction register having an output connected to the at least one data register and the boundary input/output serializer; D. a test access port having an output connected to the boundary input/output serializer and the instruction register; E. a test clock pin connected to the test access port; F. a test mode select pin connected to the test access port; G. a test data input pin connected to the instruction register, the boundary input/output serializer and the at least one data register; and H. a test data output pin selectively connected to the test access port, the instruction register, the boundary input/output serializer and the at least one data register.
Claim 15
Dependent Claim
147 words
An integrated circuit comprising: A. plural data registers; B. plural boundary input/output serializers, there being one boundary input/output serializer for each data register, each boundary input/output serializer having a control output connected to its respective data register, each boundary input/output serializer including programmable circuits; C. an instruction register having an output connected to the data registers and their respective boundary input/output serializers; D. a test access port having an output connected to the boundary input/output serializers and the instruction register; E. a test clock pin connected to the test access port; F. a test mode select pin connected to the test access port; G. a test data input pin connected to the instruction register, the boundary input/output serializers and the data registers; and H. a test data output pin selectively connected to the test access port, the instruction register, the boundary input/output serializers and the data registers.
Claim 16
Dependent Claim
147 words
An integrated circuit comprising: A. plural data registers; B. plural boundary input/output serializers, there being one boundary input/output serializer for each data register, each boundary input/output serializer having a control output connected to its respective data register, each boundary input/output serializer including programmable circuits; C. an instruction register having an output connected to the data registers and their respective boundary input/output serializers; D. a test access port having an output connected to the boundary input/output serializers and the instruction register; E. a test clock pin connected to the test access port; F. a test mode select pin connected to the test access port; G. a test data input pin connected to the instruction register, the boundary input/output serializers and the data registers; and H. a test data output pin selectively connected to the test access port, the instruction register, the boundary input/output serializers and the data registers.
Claim 17
Dependent Claim
198 words
A process of operating a data input shift register and a data output shift register with a boundary input/output serializer comprising: A. shifting a first packet of serial bits into a data input serial register via a test data input; B. updating the first packet of serial bits to an output update register; C. shifting a second packet of serial bits into a data input serial register via the test data input; D. outputting in parallel the first packet of serial bits to combinational circuits without interfering with the shifting a second packet of serial bits; E. capturing in parallel first output response data from the combinational circuits in the data output serial register; F. updating the first output response data from the data output serial register to an input update register; G. capturing in parallel second output response data from the combinational circuits in the data output serial register; H. shifting the first output response data out of the input update register in series to a test data output without interfering with the capturing in parallel second output response data; and I. controlling steps A. through H. with a boundary input/output serializer to occur at defined intervals.
Claim 18
Dependent Claim
198 words
A process of operating a data input shift register and a data output shift register with a boundary input/output serializer comprising: A. shifting a first packet of serial bits into a data input serial register via a test data input; B. updating the first packet of serial bits to an output update register; C. shifting a second packet of serial bits into a data input serial register via the test data input; D. outputting in parallel the first packet of serial bits to combinational circuits without interfering with the shifting a second packet of serial bits; E. capturing in parallel first output response data from the combinational circuits in the data output serial register; F. updating the first output response data from the data output serial register to an input update register; G. capturing in parallel second output response data from the combinational circuits in the data output serial register; H. shifting the first output response data out of the input update register in series to a test data output without interfering with the capturing in parallel second output response data; and I. controlling steps A. through H. with a boundary input/output serializer to occur at defined intervals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |