US6006024A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of routing an integrated circuit
Assignee: Apple Inc
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Filing: 1996-11-01
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Granted: 1999-12-21
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Expires: 2016-11-01
Abstract
Abstract A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.
Inventors
- 👤 Mohankumar Guruswamy
- 👤 Daniel Wesley Dulitz
- 👤 Andrea Fernandez
- 👤 Srilata Raman
- 👤 Robert L. Maziasz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:51
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
237 words
A method of routing a semiconductor device comprising the steps of: providing an integrated circuit database; routing the integrated circuit database to produce an integrated circuit layout having no ties; compacting the integrated circuit layout to form a compacted integrated circuit layout; identifying valid tie location(s) in the compacted integrated circuit layout; placing tie(s) in the valid tie location(s) in the compacted integrated circuit layout to form a modified compacted integrated circuit layout; determining if a tie coverage criteria is met; (A) when the tie coverage criteria is not met, performing the steps of: modifying and routing the integrated circuit database to produce an integrated circuit layout having at least one tie of a first tie style; repeating the steps of compacting, identifying, placing, and determining; (B) when the tie coverage criteria of step (A) is not met, performing the steps of: modifying and routing the integrated circuit database to produce an integrated circuit layout having at least one tie of a second tie style; repeating the steps of compacting, identifying, placing, and determining; when the tie coverage criteria of step (B) is not met, performing the steps of: modifying and routing the integrated circuit database to produce an integrated circuit layout having at least one tie of each of the first and second tie style; repeating the steps of compacting, identifying, placing, and determining; when the tie coverage criteria is not met generating an error message.
Claim 2
Independent Claim
237 words
A method of routing a semiconductor device comprising the steps of: providing an integrated circuit database; routing the integrated circuit database to produce an integrated circuit layout having no ties; compacting the integrated circuit layout to form a compacted integrated circuit layout; identifying valid tie location(s) in the compacted integrated circuit layout; placing tie(s) in the valid tie location(s) in the compacted integrated circuit layout to form a modified compacted integrated circuit layout; determining if a tie coverage criteria is met; (A) when the tie coverage criteria is not met, performing the steps of: modifying and routing the integrated circuit database to produce an integrated circuit layout having at least one tie of a first tie style; repeating the steps of compacting, identifying, placing, and determining; (B) when the tie coverage criteria of step (A) is not met, performing the steps of: modifying and routing the integrated circuit database to produce an integrated circuit layout having at least one tie of a second tie style; repeating the steps of compacting, identifying, placing, and determining; when the tie coverage criteria of step (B) is not met, performing the steps of: modifying and routing the integrated circuit database to produce an integrated circuit layout having at least one tie of each of the first and second tie style; repeating the steps of compacting, identifying, placing, and determining; when the tie coverage criteria is not met generating an error message.
Claim 3
Dependent Claim
24 words
The method of claim 1, wherein the first tie style is a rail tie, and the second tie style is an away channel tie.
Claim 4
Dependent Claim
23 words
The method of claim 1, wherein the first tie style is a rail tie, and the second tie style is a channel tie.
Claim 5
Dependent Claim
24 words
The method of claim 1, wherein the first tie style is an away channel tie, and the second tie style is a channel tie.
Claim 6
Independent Claim
167 words
A method of routing an integrated circuit, the method comprising the steps of: providing a first integrated circuit database; routine the first integated circuit database to produce a first integrated circuit layout having no ties; compacting the first integrated circuit layout to form a compacted integrated circuit layout; identifying a valid tie location in the compacted integrated circuit layout; wherein if no valid tie location exists, performing the steps of: providing a second integrated circuit database having a first tie, wherein the first tie has a first tie style; and routing the second integrated circuit database to produce a second integrated circuit layout having the first tie; and when determined that the second integrated circuit layout does not contain a minimum number of ties: providing a third integrated circuit database having a second tie, wherein the second tie has a second tie style different tan the first tie style; and routing the third integrated circuit database to produce a third integrated circuit layout having the second tie.
Claim 7
Independent Claim
167 words
A method of routing an integrated circuit, the method comprising the steps of: providing a first integrated circuit database; routine the first integated circuit database to produce a first integrated circuit layout having no ties; compacting the first integrated circuit layout to form a compacted integrated circuit layout; identifying a valid tie location in the compacted integrated circuit layout; wherein if no valid tie location exists, performing the steps of: providing a second integrated circuit database having a first tie, wherein the first tie has a first tie style; and routing the second integrated circuit database to produce a second integrated circuit layout having the first tie; and when determined that the second integrated circuit layout does not contain a minimum number of ties: providing a third integrated circuit database having a second tie, wherein the second tie has a second tie style different tan the first tie style; and routing the third integrated circuit database to produce a third integrated circuit layout having the second tie.
Claim 8
Dependent Claim
14 words
The method of claim 5, wherein the first tie style is a rail tie.
Claim 9
Dependent Claim
15 words
The method of claim 6, wherein the second tie style is an away channel tie.
Claim 10
Dependent Claim
14 words
The method of claim 6, wherein the second tie style is a channel tie.
Claim 11
Dependent Claim
15 words
The method of claim 5, wherein the first tie style is an away channel tie.
Claim 12
Dependent Claim
44 words
A method of manufacturing integrated circuits utilizing the method in claim 9 which further comprises: creating a set of one or more masks from the compacted integrated circuit layout; and fabricating a plurality of integrated circuits from the set of one or more masks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |