Abstract Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted "on-the-fly" during routing, increasing routing efficiency. The adjustment of routing channels in small (5 track) increments is made possible by defining "tall" macros (four transistor rows high) made of "small" (5 track high) transistors.
A gate-array-implemented integrated circuit, comprising: a gate array base having multiple transistor rows, each transistor row containing multiple transistors of a given-type, alternate transistor rows containing transistors of opposite types; a plurality of hierarchical blocks formed on said gate-array base, each including a plurality of cell placement rows, each of which has a substantially uniform height, and a plurality of routing channels separating said placement rows and containing only logic interconnections between cell placement rows; wherein placement rows in different hierarchical blocks are not aligned.
Claim 2
Dependent Claim
85 words
A gate-array-implemented integrated circuit, comprising: a gate array base having multiple transistor rows, each transistor row containing multiple transistors of a given-type, alternate transistor rows containing transistors of opposite types; a plurality of hierarchical blocks formed on said gate-array base, each including a plurality of cell placement rows, each of which has a substantially uniform height, and a plurality of routing channels separating said placement rows and containing only logic interconnections between cell placement rows; wherein placement rows in different hierarchical blocks are not aligned.
Claim 3
Dependent Claim
29 words
The apparatus of claim 1 wherein each of said placement rows contains a line extending substantially an entire length of said placement row for carrying a power supply voltage.
Claim 4
Dependent Claim
19 words
The apparatus of claim 2 further comprising a plurality of inter-block routing channels separating said plurality of hierarchical blocks.
Claim 5
Dependent Claim
40 words
The apparatus of claim 3 further comprising power interconnect lines within said inter-block routing channels for connecting lines for carrying a power supply voltage in one hierarchical block to lines for carrying a power supply voltage in another hierarchical block.
Claim 6
Dependent Claim
21 words
The apparatus of claim 4 wherein, within at least one of said hierarchical blocks, different routing channels are of different heights.