Synchronous semiconductor memory device having wave pipelining control structure and method for outputting data using the same

Claim 2

A synchronous semiconductor memory device in which data are continuously output during one cycle of a reading mode, comprising: a control unit for generating a control signal in response to first and second external clock signals, wherein said control signal is transitioned in response to either an auxiliary signal which is transitioned by detecting the rising edge of the first external clock signal or a preliminary signal which is transitioned by detecting the rising edge of the second external clock signal, whichever changes state later; and a register for storing data output from a cell array in response to said control signal.

Claim 3

A synchronous semiconductor memory device of claim 1, wherein said control unit comprises: an internal clock signal generator for generating a first internal clock signal by detecting the rising edge of the first external clock signal, and a second internal clock signal by detecting the rising edge of the second external clock signal; an auxiliary signal delay and generator for delaying the first internal clock signal and generating an auxiliary signal which is transitioned in response to the activation of the first internal clock signal; a preliminary signal delay and generator for delaying the second internal clock signal by a predetermined time which is shorter than the delay of said auxiliary signal delay and generator, and generating a preliminary signal which is transitioned in response to the activation of the second internal clock signal; and a control signal generator which receives the auxiliary signal and the preliminary signal and generates said control signal.

Claim 4

A synchronous semiconductor memory device of claim 2, wherein said auxiliary signal delay and generator comprises: a long-time delay for delaying the first internal clock signal to generate a long-time delay clock signal; and an auxiliary signal generator for generating an auxiliary signal which is transitioned in response to the activation of the long-time delay clock signal.

Claim 5

A synchronous semiconductor memory device of claim 3, wherein said auxiliary signal generator comprises: a first transmission latch gate for transmitting an auxiliary circulation signal and latching said transmitted auxiliary circulation signal when the long-time delay signal is inactive; a second transmission latch gate for transmitting the output signal of the first transmission latch gate and latching the transmitted signal when the long-time delay signal is active, to generate said auxiliary signal; and a transmission gate for transmitting the output signal of the second transmission latch gate when the long-time delay signal is inactive, to generate said auxiliary circulation signal.

Claim 6

A synchronous semiconductor memory device of claim 4, wherein said auxiliary signal generator further comprises an initializing portion for initializing said auxiliary signal after a reading mode is completed.

Claim 7

A synchronous semiconductor memory device of claim 2, wherein said preliminary signal delay and generator comprises: a short-time delay for delaying said second internal clock signal to generate a short-time delay clock signal; and a preliminary signal generator for generating said preliminary signal which is transitioned in response to the activation of the short-time delay clock signal.

Claim 8

A synchronous semiconductor memory device of claim 6, wherein said preliminary signal generator comprises: a first transmission latch gate for transmitting a preliminary circulation signal and latching the transmitted preliminary circulation signal when the short-time delay signal is inactive; a second transmission latch gate for transmitting the output signal of the first transmission latch gate and latching the transmitted signal when the short-time delay signal is active, to generate said preliminary signal; and a transmission gate for transmitting the output signal of the second transmission latch gate when the short-time delay signal is inactive, to generate said preliminary circulation signal.

Claim 9

A synchronous semiconductor memory device of claim 7, wherein said preliminary signal generator further comprises an initializing portion for initializing said preliminary signal after a reading mode is completed.

Claim 10

A synchronous semiconductor memory device of claim 2, wherein said control signal generator comprises: a transmission gate for transmitting said preliminary signal by detecting the rising edge of the first external clock signal, in response to said auxiliary signal; and a buffer for storing said signal transmitted by said transmission gate to generate a control signal.

Claim 11

A synchronous semiconductor memory device of claim 9, wherein said control signal generator further comprises an initializing portion for initializing said control signal when said auxiliary signal is inactive.

Claim 12

A synchronous semiconductor memory device of claim 1, wherein said register comprises: a transmission latch gate for transmitting the output line data when said control signal is active; and a latch for storing said signal transmitted by said transmission gate.

Claim 13

A synchronous semiconductor memory device of claim 11, wherein said register further comprises an initializing portion for initializing the output signal of said transmission gate when the power is turned on.

Claim 16

A data output method of claim 13, wherein said step (a) of generating the control signal comprises the sub-steps of: (a1) generating a first internal clock signal by detecting the rising edge of the first external clock signal and a second internal clock signal by detecting the rising edge of the second external clock signal; (a2) delaying the first internal clock signal and generating the auxiliary signal which is transitioned in response to the activation of the first internal clock signal; (a3) delaying the second internal clock signal by a predetermined time which is shorter than the delay of step (a2) and generating the preliminary signal which is transitioned in response to the activation of the second internal clock signal; and (a4) generating the control signal which is transitioned in response to either the auxiliary signal or the preliminary signal, whichever changes later, by receiving the auxiliary signal and the preliminary signal.

Claim 17

A data output method of claim 14, wherein the step (a2) comprises the sub-steps of: (a2-1) delaying the first internal clock signal to generate a long-time delay clock signal; and (a2-2) generating the auxiliary signal which is transitioned in response to the activation of the long-time delay clock signal.

Claim 18

A data output method of claim 14, wherein the step (a3) comprises the sub-steps of: (a3-1) delaying the second internal clock signal to generate a short-time delay clock signal; and (a3-2) generating the preliminary signal which is transitioned in response to the activation of the short-time delay clock signal.