Floating gate content addressable memory

Claim 2

A content addressable memory cell for use with a memory array having a bitline, a complementary bitline, a match line, and a source control line, comprising: a nonvolatile storage device coupled to the source control line, and operable to store a first data bit; an accessing circuit coupled to the storage device and the bitline, the accessing circuit operable to couple the storage device to the bitline responsive to a first control signal; a coupling circuit coupled to the storage device, the bitline, and the complementary bitline, the coupling circuit having an output and operable to couple the bitline to the output when the first data bit has a first logic level, and operable to couple the complementary bitline to the output when the first data bit has a second logic level; a biasing circuit coupled to the match line, a first predetermined voltage, and the output of the coupling circuit, the biasing circuit operable to couple the first predetermined voltage to the match line when the output of the coupling circuit is the first logic level.

Claim 3

The content addressable memory cell of claim 1, further comprising: a pull up device coupled to the storage device, the accessing circuit, and the coupling circuit, the pull up device operable to apply a second predetermined voltage to the storage device, the accessing circuit, and the coupling circuit.

Claim 4

The content addressable memory cell of claim 2 wherein the pull up device comprises a PMOS transistor having a gate operable to be coupled to the first predetermined voltage, a first input/output coupled to the second predetermined voltage, and a second input/output coupled to the storage device, the accessing circuit, and the coupling circuit.

Claim 5

The content addressable memory cell of claim 1 wherein the nonvolatile storage device comprises a floating gate transistor having a gate, a first input/output coupled to the accessing circuit and the coupling circuit, and a second input/output coupled to the source control line.

Claim 6

The content addressable memory cell of claim 1 wherein the accessing circuit comprises a transistor having a gate operable to receive the first control signal, a first input/output coupled to the bitline, and a second input/output coupled to the storage device.

Claim 7

The content addressable memory cell of claim 1 wherein the coupling circuit comprises: an NMOS transistor having a gate coupled to the storage device, a first input/output coupled to the bitline, and a second input/output coupled to the biasing circuit; a PMOS transistor having a gate coupled to the storage device, a first input/output coupled to the complementary bitline, and a second input/output coupled to the biasing circuit.

Claim 8

The content addressable memory cell of claim 1 wherein the biasing circuit comprises: an NMOS transistor having a gate coupled to the output of the coupling circuit, a first input/output coupled to the match line, and a second input/output operable to be coupled to the first predetermined voltage.

Claim 9

The content addressable memory cell of claim 1 wherein the first logic level comprises a logic "1" and the second logic level comprises a logic "0."

Claim 10

The content addressable memory cell of claim 1 wherein the first predetermined voltage comprises ground.

Claim 11

The content addressable memory cell of claim 2 wherein the second predetermined voltage comprises V DD .

Claim 12

The content addressable memory cell of claim 2, further comprising: an inverter having an input coupled to the storage device and an output coupled to the pull up device; and a second accessing circuit coupled to the output of the inverter, the coupling circuit, and the complementary bitline, the second accessing circuit operable to couple the complementary bitline to the coupling circuit in response to the first control signal.

Claim 13

The content addressable memory cell of claim 11 wherein the pull up device comprises a PMOS transistor having a gate coupled to the output of the inverter, a first input/output operable to the second predetermined voltage, and a second input/output coupled to the storage device.

Claim 14

The content addressable memory cell of claim 11 wherein the second accessing circuit comprises an NMOS transistor having a gate operable to receive the first control signal, a first input/output coupled to the complementary bitline, and a second input/output coupled to the output of the inverter and the coupling circuit.

Claim 15

The content addressable memory cell of claim 11 wherein the coupling circuit comprises: a first NMOS transistor having a gate coupled to the storage device, a first input/output coupled to the bitline, and a second input/output coupled to the biasing circuit; a second NMOS transistor having a gate coupled to the output of the inverter and the second accessing circuit, a first input/output coupled to the complementary bitline, and a second input/output coupled to the biasing circuit.

Claim 16

A content addressable memory cell for use with a memory array having a bitline, a complementary bitline, a match line, and a source control line, comprising: a floating gate transistor coupled to the source control line, and operable to store a first data bit; an accessing circuit coupled to the storage device and the bitline, the accessing circuit operable to couple the storage device to the bitline responsive to a first control signal; an enable signal generator coupled to the storage device, the bitline, and the complementary bitline, the enable signal generator operable to generate an enabling signal when the value of a second data bit on the bitline matches the value of the first data bit stored in the nonvolatile storage device; and a biasing circuit coupled to the enable signal generator to receive the enabling signal and to the match line, the biasing element operable to bias the match line to a first predetermined voltage responsive to receiving the enabling signal.

Claim 17

A content addressable memory cell for use with a memory array having a bitline, a complementary bitline, a match line, and a source control line, comprising: a floating gate transistor coupled to the source control line, and operable to store a first data bit; an accessing circuit coupled to the storage device and the bitline, the accessing circuit operable to couple the storage device to the bitline responsive to a first control signal; an enable signal generator coupled to the storage device, the bitline, and the complementary bitline, the enable signal generator operable to generate an enabling signal when the value of a second data bit on the bitline matches the value of the first data bit stored in the nonvolatile storage device; and a biasing circuit coupled to the enable signal generator to receive the enabling signal and to the match line, the biasing element operable to bias the match line to a first predetermined voltage responsive to receiving the enabling signal.

Claim 18

The content addressable memory cell of claim 15, further comprising: a pull up device coupled to the storage device, the accessing circuit, and the coupling circuit, the pull up device operable to apply a second predetermined voltage to the storage device, the accessing circuit, and the enable signal generator.

Claim 19

The content addressable memory cell of claim 15 wherein the enable signal generator is operable to generate the enabling signal when the complement of the value of the first data bit stored in storage device matches the value of a third data bit on the complementary bitline.

Claim 20

The content addressable memory cell of claim 15 wherein the storage device comprises a floating gate transistor having a gate, a first input/output coupled to the accessing circuit and the enable signal generator, and a second input/output coupled to the source control line.

Claim 21

A content addressable memory cell for use with a memory array having a bitline, a complementary bitline, a match line, and a source control line, comprising: a floating gate transistor having a first input/output, a second input/output, and a gate operable to receive a first control signal; a first PMOS transistor having a gate coupled to a first voltage source, a first input/output coupled to a second voltage source, and a second input/output coupled to the first input/output of the floating gate transistor; a first NMOS transistor having a gate operable to receive a second control signal, a first input/output coupled to the bitline, and a second input/output coupled to the first input/output of the floating gate transistor; a second NMOS transistor having a gate coupled to the first input/output of the floating gate transistor, a first input/output coupled to the bitline, and a second input/output; a second PMOS transistor having a gate coupled to the first input/output of the floating gate transistor, a first input/output coupled to the complementary bitline, and a second input/output coupled to the second input output of the second NMOS transistor; a third NMOS transistor having a gate coupled to the second input/output of the second NMOS transistor, a first input/output coupled to the first voltage source, and a second input/output coupled to the match line.

Claim 22

A content addressable memory cell for use with a memory array having a bitline, a complementary bitline, a match line, and a source control line, comprising: a floating gate transistor having a first input/output, a second input/output, and a gate operable to receive a first control signal; a first PMOS transistor having a gate coupled to a first voltage source, a first input/output coupled to a second voltage source, and a second input/output coupled to the first input/output of the floating gate transistor; a first NMOS transistor having a gate operable to receive a second control signal, a first input/output coupled to the bitline, and a second input/output coupled to the first input/output of the floating gate transistor; a second NMOS transistor having a gate coupled to the first input/output of the floating gate transistor, a first input/output coupled to the bitline, and a second input/output; a second PMOS transistor having a gate coupled to the first input/output of the floating gate transistor, a first input/output coupled to the complementary bitline, and a second input/output coupled to the second input output of the second NMOS transistor; a third NMOS transistor having a gate coupled to the second input/output of the second NMOS transistor, a first input/output coupled to the first voltage source, and a second input/output coupled to the match line.

Claim 23

A content addressable memory array, comprising: a plurality of memory cells, arranged in rows and columns; a word line coupled to each cell in a first row; a bitline coupled to each cell in a first column; a match line coupled to each memory cell in the array; a floating gate transistor within each memory cell in the array; an access transistor within each memory cell coupled to the bitline and the floating gate transistor to operably couple the bitline to the floating gate memory; and a biasing transistor within each memory cell coupled to the match line and to a coupling circuit that is coupled to the floating gate transistor, the biasing circuit operable to couple a first predetermined voltage to the match line when an output of the coupling circuit is at a first logic level.

Claim 24

A content addressable memory array, comprising: a plurality of memory cells, arranged in rows and columns; a word line coupled to each cell in a first row; a bitline coupled to each cell in a first column; a match line coupled to each memory cell in the array; a floating gate transistor within each memory cell in the array; an access transistor within each memory cell coupled to the bitline and the floating gate transistor to operably couple the bitline to the floating gate memory; and a biasing transistor within each memory cell coupled to the match line and to a coupling circuit that is coupled to the floating gate transistor, the biasing circuit operable to couple a first predetermined voltage to the match line when an output of the coupling circuit is at a first logic level.

Claim 25

The array according to claim 20 wherein said match line is coupled to each memory cell in said first row.

Claim 26

The array according to claim 20 wherein said match line is coupled to each memory cell in said first column.

Claim 27

The array according to claim 20, further including a source access line coupled to each memory cell in the first row and each memory cell in an adjacent row to the first row such that each floating gate transistor in both said first and second rows have a common source line.

Claim 28

The array according to claim 20, further including a select gate line coupled to each memory cell in the first row.

Claim 29

The array according to claim 20, further including a select gate line individually coupled to each memory cell in the array.

Claim 30

The array according to claim 20, further including a select gate line coupled to each memory cell in the first column.

Claim 33

The method of claim 21, further comprising: applying the complement of the address bit to the complementary bitline; comparing the logic level of the bit applied to the complementary bitline with the logic level stored in the floating gate transistor; and generating the match signal when the logic level applied to the complementary bitline corresponds to the complement of the logic level stored in the floating gate transistor.