US5998822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit and a method of manufacturing the same
Assignee: UMC Japan Co Ltd
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Filing: 1997-11-25
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Granted: 1999-12-07
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Expires: 2017-11-25
Abstract
Abstract Dielectric isolation in the bit-line direction is performed by a first trench filled with an insulator, dielectric isolation in the word-line direction is performed by a second trench filled with a conductive film serving as a field-shield electrode interposing an insulating film, and capacitors are formed on side walls of the second trench by the conductive film and a semiconductor substrate with the insulating film interposed therebetween. A high-density, large-scale DRAM is realized by combining the technologies of field-shield element isolation, trench element isolation, and side-wall capacitors in a trench. In this DRAM, the conductive film in a trench-capacitor structure serves as a field-shield electrode in a field-shield structure for dielectric isolation between memory cells. Since the capacitor forms a capacitance inside the semiconductor substrate on one side wall of the trench, high-density integration is possible. This further increases the density and the scale of a semiconductor integrated circuit.
Inventors
- 👤 Toshio Wada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/051; H10W10/10; H10W10/17; H10W10/50
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
124 words
A semiconductor integrated circuit in which a plurality of memory cells having transistors and capacitors are arranged in a matrix manner on one major surface of a semiconductor substrate, comprising: a trench formed in said semiconductor substrate between said memory cells adjacent to each other; and a conductive film filling said trench with an insulating film intervening, the insulating film covering inner wall of said trench, wherein said conductive film is a field-shield electrode for dielectrically isolating said memory cells adjacent to each other across said trench, capacitively coupled with said semiconductor substrate in said memory cells at side-wall portions of said trench through said insulating film, and constituting said capacitors of said memory cells together with said semiconductor substrate and said insulating film.
Claim 2
Dependent Claim
124 words
A semiconductor integrated circuit in which a plurality of memory cells having transistors and capacitors are arranged in a matrix manner on one major surface of a semiconductor substrate, comprising: a trench formed in said semiconductor substrate between said memory cells adjacent to each other; and a conductive film filling said trench with an insulating film intervening, the insulating film covering inner wall of said trench, wherein said conductive film is a field-shield electrode for dielectrically isolating said memory cells adjacent to each other across said trench, capacitively coupled with said semiconductor substrate in said memory cells at side-wall portions of said trench through said insulating film, and constituting said capacitors of said memory cells together with said semiconductor substrate and said insulating film.
Claim 3
Dependent Claim
40 words
A circuit according to claim 1, wherein said semiconductor substrate is constituted by a heavily doped silicon single-crystal substrate of one conductivity type and a lightly doped epitaxial layer of the same conductivity type formed on said silicon single-crystal substrate.
Claim 4
Dependent Claim
22 words
A circuit according to claim 2, wherein said trench has a depth to reach said silicon single-crystal substrate through said epitaxial layer.
Claim 5
Dependent Claim
71 words
A circuit according to claim 1, wherein said memory cells are formed in intersections of bit lines extending in a row direction and word lines extending in a column direction and constitute a memory cell array, and said trenches extend substantially parallel to said word lines, and said memory cells between said trenches are dielectrically isolated by other trenches extending substantially parallel to said bit lines and filled with an insulator.
Claim 6
Dependent Claim
20 words
A circuit according to claim 1, wherein a potential of said field-shield electrode is a potential of an external power-supply.
Claim 7
Dependent Claim
21 words
A circuit according to claim 1, wherein a potential of said field-shield electrode is a reference potential of an external power-supply.
Claim 8
Dependent Claim
21 words
A circuit according to claim 2, wherein a potential of said field-shield electrode is a potential of said silicon single-crystal substrate.
Claim 9
Dependent Claim
41 words
A circuit according to claim 2 further comprising, conductive regions formed in said side-wall portions of said trench in said epitaxial layer, and wherein said conductive regions are electrically connected to at least one of drains and sources of said transistors.
Claim 10
Dependent Claim
21 words
A circuit according to claim 8, wherein said conductive region is two-layer structure constituted by diffusion regions having different conductivity types.
Claim 11
Dependent Claim
15 words
A circuit according to claim 1, wherein side-wall surfaces of said trench are roughened surfaces.
Claim 12
Dependent Claim
20 words
A circuit according to claim 10, wherein said roughened surfaces are is formed by crystal grains of poly crystal silicon.
Claim 13
Dependent Claim
40 words
A circuit according to claim 10, wherein said semiconductor substrate is constituted by a heavily doped silicon single-crystal substrate of one conductivity type and a lightly doped epitaxial layer of the same conductivity type formed on said silicon single-crystal substrate.
Claim 14
Dependent Claim
22 words
A circuit according to claim 12, wherein said trench has a depth to reach said silicon single-crystal substrate through said epitaxial layer.
Claim 15
Dependent Claim
71 words
A circuit according to claim 10, wherein said memory cells are formed at intersections of bit lines extending in a row direction and word lines extending in a column direction and constitute a memory cell array, and said trenches extend substantially parallel to said word lines, and said memory cells between said trenches are dielectrically isolated by other trenches extending substantially parallel to said bit lines and filled with an insulator.
Claim 16
Dependent Claim
20 words
A circuit according to claim 10, wherein a potential of said field-shield electrode is a potential of an external power-supply.
Claim 17
Dependent Claim
21 words
A circuit according to claim 10, wherein a potential of said field-shield electrode is a reference potential of an external power-supply.
Claim 18
Dependent Claim
21 words
A circuit according to claim 12, wherein a potential of said field-shield electrode is a potential of said silicon single-crystal substrate.
Claim 19
Dependent Claim
44 words
A circuit according to claim 12 further comprising, conductive regions formed in portions close to said side-wall portions of said trench in said epitaxial layer, and wherein said conductive regions are electrically connected to at least one of drains and sources of said transistors.
Claim 20
Dependent Claim
21 words
A circuit according to claim 18, wherein said conductive region is two-layer structure constituted by diffusion regions having different conductivity types.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-06 | 2003-06-07 | 2003-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-06 | 2007-06-07 | 2007-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-06 | 2011-06-07 | 2011-12-07 | $7700.00 | Window Closed / Lapsed |