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US5998274A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor

Assignee: Micron Technology Inc
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Filing: 1998-10-14
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Granted: 1999-12-07
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Expires: 2018-10-14
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Abstract

Abstract A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

Inventors

  • 👤 Salman Akram
  • 👤 Akram Ditali

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 10:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/021

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 169 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first and second contact subregions within the second contact region, each contact subregion having a dopant concentration that differs from that of the other contact subregion; and forming an anti-punchthrough region underlying the second contact region, wherein the step of forming the anti-punchthrough region comprises the step of forming a first anti-punchthrough subregion and the step of forming a second anti-punchthrough subregion, wherein the first anti-punchthrough subregion is formed below and in alignment with the first contact subregion, and wherein the second anti-punchthrough subregion is formed below and in alignment with the second contact subregion, each anti-punchthrough subregion having a dopant concentration that differs from that of the other anti-punchthrough subregion.
Claim 2
Independent Claim 169 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first and second contact subregions within the second contact region, each contact subregion having a dopant concentration that differs from that of the other contact subregion; and forming an anti-punchthrough region underlying the second contact region, wherein the step of forming the anti-punchthrough region comprises the step of forming a first anti-punchthrough subregion and the step of forming a second anti-punchthrough subregion, wherein the first anti-punchthrough subregion is formed below and in alignment with the first contact subregion, and wherein the second anti-punchthrough subregion is formed below and in alignment with the second contact subregion, each anti-punchthrough subregion having a dopant concentration that differs from that of the other anti-punchthrough subregion.
Claim 3
Independent Claim 194 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third contact subregions within the second contact region, each contact subregion having a dopant concentration that differs from that of the other two contact subregions; and forming an anti-punchthrough region underlying the second contact region, wherein the step of forming the anti-punchthrough region comprises the step of forming a first anti-punchthrough subregion, the step of forming a second anti-punchthrough subregion, and the step of forming a third anti-punchthrough subregion, wherein the first anti-punchthrough subregion is formed below and in alignment with the first contact subregion, the second anti-punchthrough subregion is formed below and in alignment with the second contact subregion, and the third anti-punchthrough subregion is formed below and in alignment with the third contact subregion, each anti-punchthrough subregion having a dopant concentration that differs from that of the other two anti-punchthrough subregions.
Claim 4
Independent Claim 194 words
A method of forming a transistor on a substrate, comprising the following steps: forming a dielectric layer overlying the substrate; forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate; forming first, second and third contact subregions within the second contact region, each contact subregion having a dopant concentration that differs from that of the other two contact subregions; and forming an anti-punchthrough region underlying the second contact region, wherein the step of forming the anti-punchthrough region comprises the step of forming a first anti-punchthrough subregion, the step of forming a second anti-punchthrough subregion, and the step of forming a third anti-punchthrough subregion, wherein the first anti-punchthrough subregion is formed below and in alignment with the first contact subregion, the second anti-punchthrough subregion is formed below and in alignment with the second contact subregion, and the third anti-punchthrough subregion is formed below and in alignment with the third contact subregion, each anti-punchthrough subregion having a dopant concentration that differs from that of the other two anti-punchthrough subregions.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-12-06 2003-06-07 2003-12-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-12-06 2007-06-07 2007-12-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-12-06 2011-06-07 2011-12-07 $7700.00 Window Closed / Lapsed

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