Patent US5996058A successfully refreshed from Google Patents.
US5996058A
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System and method for handling software interrupts with argument passing
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-08-19
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Granted: 1999-11-30
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Expires: 2016-08-19
Abstract
Abstract A multiprocessor architectural definition provides that a program executing on a first processor interrupts a second processor by executing a software interrupt instruction. The software interrupt instruction includes an argument field for passing information from a program requesting the software interrupt. The argument, along with the opcode, is saved in a register designated for holding the argument. The information communicated via the argument is used in one embodiment to indicate a cause of the interrupt. In an embodiment, the information communicated via the argument designates an interrupt service routine to be activated in the interrupted processor.
Inventors
- 👤 Seungyeon Peter Song
- 👤 Moataz A. Mohamed
- 👤 Heon-chul Park
- 👤 Le Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:00
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F15/17; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/38; G06F9/3877; G06F9/3879; G06F9/3885; G06F9/3887; G06F9/3888
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
104 words
A computer system comprising: a plurality of processors including a first processor and a second processor, the first processor and the second processor being mutually asymmetric with dissimilar control-handling and data-handling characteristics; the first processor including a control logic for executing a software interrupt instruction that evokes a software interrupt in the second processor then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor; the second processor including a control logic responsive to the software interrupt for accessing the information of the argument field.
Claim 2
Dependent Claim
104 words
A computer system comprising: a plurality of processors including a first processor and a second processor, the first processor and the second processor being mutually asymmetric with dissimilar control-handling and data-handling characteristics; the first processor including a control logic for executing a software interrupt instruction that evokes a software interrupt in the second processor then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor; the second processor including a control logic responsive to the software interrupt for accessing the information of the argument field.
Claim 3
Dependent Claim
35 words
A computer system according to claim 1 wherein the software interrupt instruction argument field includes a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.
Claim 4
Dependent Claim
51 words
A computer system according to claim 1 wherein the software interrupt instruction argument field includes a field for transferring information identifying an instruction code within a storage in the second processor at which a software interrupt servicing routine is located, the software interrupt servicing routine being activated by the software interrupt.
Claim 5
Dependent Claim
40 words
A computer system according to claim 1 wherein the software interrupt instruction is a JOIN instruction causing a software interrupt in the second processor and activating a software interrupt servicing routine identified by an offset argument in the argument field.
Claim 6
Dependent Claim
34 words
A computer system according to claim 4 wherein the JOIN instruction argument field includes a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.
Claim 7
Dependent Claim
30 words
A computer system according to claim 4 wherein the JOIN instruction argument field holds an offset argument indicative of a branch address for branching to a software interrupt servicing routine.
Claim 8
Dependent Claim
48 words
A computer system according to claim 1 wherein: the second processor is a control processor having a defined data path width; and the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.
Claim 9
Dependent Claim
39 words
A computer system according to claim 1 wherein: the first processor control logic for executing a software interrupt instruction evoking a software interrupt in the second processor further includes control logic deactivating the first processor to an idle state.
Claim 10
Dependent Claim
67 words
A computer system according to claim 1 wherein an interrupt and exception subhandler operating on a second processor responds to an interrupt or exception on the first processor for handling the interrupt and exception conditions of the first processor in a first execution thread and the second processor in a second execution thread, the first and second execution threads being controlled in combination by the second processor.
Claim 11
Dependent Claim
30 words
A computer system according to claim 1 further comprising: a coprocessor coupled between the first processor and the second processor, the coprocessor including a register for holding the argument field.
Claim 12
Dependent Claim
86 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt ind exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, the argument field including a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.
Claim 13
Dependent Claim
86 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt ind exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, the argument field including a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.
Claim 14
Dependent Claim
102 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, the argument field including a field for transferring information identifying an instruction code within a storage in the second processor at which a software interrupt servicing routine is located, the software interrupt servicing routine being activated by the software interrupt.
Claim 15
Dependent Claim
102 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, the argument field including a field for transferring information identifying an instruction code within a storage in the second processor at which a software interrupt servicing routine is located, the software interrupt servicing routine being activated by the software interrupt.
Claim 16
Dependent Claim
95 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein the software interrupt instruction is a JOIN instruction causing a software interrupt in the second processor and activating a software interrupt servicing routine identified by an offset argument in the argument field.
Claim 17
Dependent Claim
95 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein the software interrupt instruction is a JOIN instruction causing a software interrupt in the second processor and activating a software interrupt servicing routine identified by an offset argument in the argument field.
Claim 18
Dependent Claim
34 words
A first processor according to claim 13 wherein the JOIN instruction argument field includes a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.
Claim 19
Dependent Claim
30 words
A first processor according to claim 13 wherein the JOIN instruction argument field holds an offset argument indicative of a branch address for branching to a software interrupt servicing routine.
Claim 20
Dependent Claim
103 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein: the second processor is a control processor having a defined data path width; and the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.
Claim 21
Dependent Claim
103 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein: the second processor is a control processor having a defined data path width; and the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.
Claim 22
Dependent Claim
97 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein: the first processor control logic is capable of executing a software interrupt instruction evoking a software interrupt in the second processor and further includes control logic deactivating the first processor to an idle state.
Claim 23
Dependent Claim
97 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein: the first processor control logic is capable of executing a software interrupt instruction evoking a software interrupt in the second processor and further includes control logic deactivating the first processor to an idle state.
Claim 24
Dependent Claim
122 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein an interrupt and exception subhandler operating on a second processor responds to an interrupt or exception on the first processor for handling the interrupt and exception conditions of the first processor in a first execution thread and the second processor in a second execution thread, the first and second execution threads being controlled in combination by the second processor.
Claim 25
Dependent Claim
122 words
A first processor in a multiple processor computer system comprising: a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor; the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein an interrupt and exception subhandler operating on a second processor responds to an interrupt or exception on the first processor for handling the interrupt and exception conditions of the first processor in a first execution thread and the second processor in a second execution thread, the first and second execution threads being controlled in combination by the second processor.
Claim 26
Independent Claim
108 words
A method of operating a computer system comprising: operating a plurality of processors including a first processor and a second processor, the first processor and the second processor being mutually asymmetric with dissimilar control-handling and data-handling characteristics; executing a software interrupt instruction on the first processor that evokes a software interrupt in the second processor; deferring to the second processor control of interrupt and exception handling operations controlling the first processor; passing information from the first processor to the second processor via the software interrupt instruction having an argument field; and accessing the information of the argument field in the second processor in response to the software interrupt.
Claim 27
Independent Claim
108 words
A method of operating a computer system comprising: operating a plurality of processors including a first processor and a second processor, the first processor and the second processor being mutually asymmetric with dissimilar control-handling and data-handling characteristics; executing a software interrupt instruction on the first processor that evokes a software interrupt in the second processor; deferring to the second processor control of interrupt and exception handling operations controlling the first processor; passing information from the first processor to the second processor via the software interrupt instruction having an argument field; and accessing the information of the argument field in the second processor in response to the software interrupt.
Claim 28
Dependent Claim
35 words
A method according to claim 19 further comprising: transferring information identifying a condition within the first processor for evoking an interrupt in the second processor via a field in the software interrupt instruction argument field.
Claim 29
Dependent Claim
51 words
A method according to claim 19 further comprising: transferring information identifying an instruction code within a storage in the second processor at which a software interrupt servicing routine is located via a field in the software interrupt instruction argument field; and activating the software interrupt servicing routine by the software interrupt.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |