US5995993A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial in-circuit emulator
Assignee: Winbond Electronics Corp
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Filing: 1998-01-05
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Granted: 1999-11-30
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Expires: 2018-01-05
Abstract
Abstract To debug software programs, an economical and efficient serial in-circuit emulator (ICE) according to the invention can pause the operation of a CPU to read/write current data from/to a register of the CPU or to modify the current data in a register of the CPU. Furthermore, this serial in-circuit emulator can also read/write current data from/to an external memory or other external devices, or modify these data. The CPU mentioned above has an instruction register and a debugging register which allows the serial in-circuit emulator to read/write required data. This serial in-circuit emulator, which comprises a serial in-circuit emulator control register, a serial in-circuit emulator address register and a serial data input/output terminal, can be easily integrated with the CPU without affecting the operating speed thereof as well as has all functions that conventional serial in-circuit emulators should provide.
Inventors
- 👤 C. J. Liang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3652
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
292 words
A serial in-circuit emulator which can pause the operation of a CPU to read/write or modify the data of a register of said CPU, an external memory or an external device, wherein said CPU has an instruction register and a debugging register by which said serial in-circuit emulator can read/write required data, comprising: a serial in-circuit emulator control register for controlling said CPU, which includes: a first flag region connected to said CPU to reset said CPU; a second flag region connected to said CPU to force said CPU to enter a temporarily halted state; a third flag region connected to said CPU to force said CPU's pipeline to jump to a next stage; a fourth flag region connected to said CPU to force said CPU to return to a normal state; a fifth flag region and sixth flag region connected to said CPU to identify whether said CPU is in a normal state, an external memory bus cycle state or a temporarily halted state; a seventh flag region connected to said CPU to check whether the data of said external memory or external device are transferred to said register, or the data of said register are transferred to said external memory or external device; an eighth flag region connected to said CPU to check whether the data of said debugging register are transferred to said register or the data of said register are transferred to said debugging register; a serial in-circuit emulator address register which can address said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register to read/write required data; and a serial data input/output terminal connected to said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register.
Claim 2
Dependent Claim
292 words
A serial in-circuit emulator which can pause the operation of a CPU to read/write or modify the data of a register of said CPU, an external memory or an external device, wherein said CPU has an instruction register and a debugging register by which said serial in-circuit emulator can read/write required data, comprising: a serial in-circuit emulator control register for controlling said CPU, which includes: a first flag region connected to said CPU to reset said CPU; a second flag region connected to said CPU to force said CPU to enter a temporarily halted state; a third flag region connected to said CPU to force said CPU's pipeline to jump to a next stage; a fourth flag region connected to said CPU to force said CPU to return to a normal state; a fifth flag region and sixth flag region connected to said CPU to identify whether said CPU is in a normal state, an external memory bus cycle state or a temporarily halted state; a seventh flag region connected to said CPU to check whether the data of said external memory or external device are transferred to said register, or the data of said register are transferred to said external memory or external device; an eighth flag region connected to said CPU to check whether the data of said debugging register are transferred to said register or the data of said register are transferred to said debugging register; a serial in-circuit emulator address register which can address said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register to read/write required data; and a serial data input/output terminal connected to said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register.
Claim 3
Dependent Claim
20 words
A serial in-circuit emulator as claimed in claim 1, wherein said serial in-circuit emulator can transmit data parallel-to-serial and serial-to-parallel.
Claim 4
Dependent Claim
42 words
A serial in-circuit emulator as claimed in claim 1, wherein each of said first flag region, second flag region, third flag region, fourth flag region, fifth flag region, sixth flag region, seventh flag region and eighth flag region consists of one bit.
Claim 5
Dependent Claim
24 words
A serial in-circuit emulator as claimed in claim 3, wherein when said first flag region is a logic level "1", said CPU is reset.
Claim 6
Dependent Claim
30 words
A serial in-circuit emulator as claimed in claim 3, wherein when said second flag region is a logic level "1," said CPU is forced to enter said temporarily halted state.
Claim 7
Dependent Claim
31 words
A serial in-circuit emulator as claimed in claim 3, wherein when said third flag region is a logic level "1," said CPU's pipeline is forced to jump to the next stage.
Claim 8
Dependent Claim
30 words
A serial in-circuit emulator as claimed in claim 3, wherein when said fourth flag region is a logic level "1," said CPU is forced to return to said normal state.
Claim 9
Dependent Claim
36 words
A serial in-circuit emulator as claimed in claim 3, wherein when said fifth flag region and sixth flag region are logic levels "0" and "0" respectively, it means that said CPU is in said normal state.
Claim 10
Dependent Claim
39 words
A serial in-circuit emulator as claimed in claim 3, wherein when said fifth flag reign and sixth flag region are logic levels "0" and "1," respectively, it means that said CPU is in said external memory bus cycle state.
Claim 11
Dependent Claim
37 words
A serial in-circuit emulator as claimed in claim 3, wherein when said fifth flag region and sixth flag region are logic levels "1" and "0," respectively, it means that said CPU is in said temporarily halted state.
Claim 12
Dependent Claim
52 words
A serial in-circuit emulator as claimed in claim 3, wherein when said seven flag region is a logic level "1," it means that the data of said external memory or external device are transferred to said register, or the data of said register are transferred to said external memory or external device.
Claim 13
Dependent Claim
46 words
A serial in-circuit emulator as claimed in claim 3, wherein when said eighth flag region is a logic level "1," it means that the data of said debugging register are transferred to said register, or the data of said register are transferred to said debugging register.
Claim 14
Dependent Claim
20 words
A serial in-circuit emulator as claimed in claim 1, wherein said serial in-circuit emulator address register consists of 2 bits.
Claim 15
Dependent Claim
280 words
A serial in-circuit emulator which can pause the operation of a CPU to read/write or modify the data of a register of said CPU, external memory or external device, wherein said CPU has an instruction register and a debugging register by which said serial in-circuit emulator can read/write required data, comprising: a serial in-circuit emulator control register for controlling said CPU, which includes: a first flag connected to said CPU to reset said CPU; a second flag connected to said CPU to force said CPU to enter a temporarily-stopping state; a third flag connected to said CPU to force said CPU's pipeline to jump to the next stage; a fourth flag connected to said CPU to force said CPU to return to a normal state; a fifth flag and sixth flag connected to said CPU to identify whether said CPU is in a normal state, an external memory period state or a temporarily halted state; a seven flag connected to said CPU to check whether the data of said external memory or external device are transferred to said register, or the data of said register are transferred to said external memory or external device; an eighth flag connected to said CPU to check whether the data of said debugging register are transferred to said register or the data of said register are transferred to said debugging register; a serial in-circuit emulator address register which can address said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register to read/write required data; and a serial data input/output terminal connected to said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register.
Claim 16
Dependent Claim
280 words
A serial in-circuit emulator which can pause the operation of a CPU to read/write or modify the data of a register of said CPU, external memory or external device, wherein said CPU has an instruction register and a debugging register by which said serial in-circuit emulator can read/write required data, comprising: a serial in-circuit emulator control register for controlling said CPU, which includes: a first flag connected to said CPU to reset said CPU; a second flag connected to said CPU to force said CPU to enter a temporarily-stopping state; a third flag connected to said CPU to force said CPU's pipeline to jump to the next stage; a fourth flag connected to said CPU to force said CPU to return to a normal state; a fifth flag and sixth flag connected to said CPU to identify whether said CPU is in a normal state, an external memory period state or a temporarily halted state; a seven flag connected to said CPU to check whether the data of said external memory or external device are transferred to said register, or the data of said register are transferred to said external memory or external device; an eighth flag connected to said CPU to check whether the data of said debugging register are transferred to said register or the data of said register are transferred to said debugging register; a serial in-circuit emulator address register which can address said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register to read/write required data; and a serial data input/output terminal connected to said serial in-circuit emulator control register, said instruction register of said CPU, and said debugging register.
Claim 17
Dependent Claim
20 words
A serial in-circuit emulator as claimed in claim 14, wherein said serial in-circuit emulator can transmit data parallel-to-serial and serial-to-parallel.
Claim 18
Dependent Claim
23 words
A serial in-circuit emulator as claimed in claim 14, wherein when said first flag is a logic level "1," said CPU is reset.
Claim 19
Dependent Claim
29 words
A serial in-circuit emulator as claimed in claim 14, wherein when said second flag is a logic level "1," said CPU is forced to enter said temporarily halted state.
Claim 20
Dependent Claim
30 words
A serial in-circuit emulator as claimed in claim 14, wherein when said third flag is a logic level "1," said CPU's pipeline is forced to jump to the next stage.
Claim 21
Dependent Claim
29 words
A serial in-circuit emulator as claimed in claim 14, wherein when said fourth flag is a logic level "1," said CPU is forced to return to said normal state.
Claim 22
Dependent Claim
34 words
A serial in-circuit emulator as claimed in claim 14, wherein when said fifth flag and sixth flag are logic levels "0" and "0," respectively, it means that said CPU is in said normal state.
Claim 23
Dependent Claim
37 words
A serial in-circuit emulator as claimed in claim 14, wherein when said fifth flag and sixth flag are logic levels "0" and "1," respectively, it means that said CPU is in said external memory bus cycle state.
Claim 24
Dependent Claim
35 words
A serial in-circuit emulator as claimed in claim 14, wherein when said fifth flag and sixth flag are logic levels "1" and "0," respectively, it means that said CPU is in said temporarily halted state.
Claim 25
Dependent Claim
51 words
A serial in-circuit emulator as claimed in claim 14, wherein when said seven flag is a logic level "1," it means that the data of said external memory or external device are transferred to said register, or the data of said register are transferred to said external memory or external device.
Claim 26
Dependent Claim
45 words
A serial in-circuit emulator as claimed in claim 14, wherein when said eighth flag is a logic level "1," it means that the data of said debugging register are transferred to said register, or the data of said register are transferred to said debugging register.
Claim 27
Dependent Claim
20 words
A serial in-circuit emulator as claimed in claim 14, wherein said serial in-circuit emulator address register consists of 2 bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |