Circuit for burn-in operation on a wafer of memory devices

Claim 1

A burn-in circuit provided on a wafer formed with a plurality of dice on each of which a memory device is formed and which dice are separated by a plurality of scribe lines, the burn-in circuit being used for burn-in operation on each memory device on the wafer, the burn-in circuit comprising: a test circuit incorporated in the memory device; a first pad, formed in one of the scribe lines, for connecting an externally generated burn-in enable signal to the test circuit in the memory device; and a second pad, formed in one of the scribe lines, for connecting an externally generated DC bias voltage to the memory device; wherein the test circuit performs a burn-in operation on the associated memory device at a region during a burn-in test procedure in response to the burn-in enable signal, wherein the region of the associated memory device at least includes memory cells and a periphery circuit, and the periphery circuit at least includes word lines, bit lines, a column sense amplifier, and a row decoder.

Claim 8

A method for performing a burn-in test procedure on a semiconductor wafer formed with a plurality of dice, on each of which a memory device is formed, which the dice are separated by a plurality of scribe lines, and each of which the dice includes means for generating row addresses, column addresses, and associated word lines, the method comprising the steps of: forming a test circuit on each of the dice to generate signals, which are used to control a burn-in operation on each of memory cells and a periphery circuit in a single burn-in test procedure; forming a first pad and a second pad in one of the scribe lines; connecting the first pad to the test circuit in each of the dice; connecting the second pad to a bias input end of each of the dice; generating and transferring an externally generated DC bias voltage via the second pad to the bias input end of each of the dice; generating and transferring an externally generated burn-in enable signal via the first pad to the test circuit in each of the dice, wherein the burn-in enable signal triggers the test circuit to generate a burn-in oscillating signal; converting the burn-in oscillating signal into a plurality of pulse trains which are used for the burn-in operation on the periphery circuit of the memory device other than the memory cells, wherein all addresses with respect to the memory cells of the memory device can be generated after logic combination of the pulse trains; and transferring the burn-in enable signal to a column sense amplifier and a row decoder of the memory device, so as to enable the column sense amplifier and disable the row decoder, and further enable the word lines and the row addresses and disable the column addresses and so as to perform the burn-in operation on the memory cells of the memory device.

Claim 9

A method for performing a burn-in test procedure on a semiconductor wafer formed with a plurality of dice, on each of which a memory device is formed, which the dice are separated by a plurality of scribe lines, and each of which the dice includes means for generating row addresses, column addresses, and associated word lines, the method comprising the steps of: forming a test circuit on each of the dice to generate signals, which are used to control a burn-in operation on each of memory cells and a periphery circuit in a single burn-in test procedure; forming a first pad and a second pad in one of the scribe lines; connecting the first pad to the test circuit in each of the dice; connecting the second pad to a bias input end of each of the dice; generating and transferring an externally generated DC bias voltage via the second pad to the bias input end of each of the dice; generating and transferring an externally generated burn-in enable signal via the first pad to the test circuit in each of the dice, wherein the burn-in enable signal triggers the test circuit to generate a burn-in oscillating signal; converting the burn-in oscillating signal into a plurality of pulse trains which are used for the burn-in operation on the periphery circuit of the memory device other than the memory cells, wherein all addresses with respect to the memory cells of the memory device can be generated after logic combination of the pulse trains; and transferring the burn-in enable signal to a column sense amplifier and a row decoder of the memory device, so as to enable the column sense amplifier and disable the row decoder, and further enable the word lines and the row addresses and disable the column addresses and so as to perform the burn-in operation on the memory cells of the memory device.