Patent US5995210A successfully refreshed from Google Patents.
US5995210A
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Integrated architecture for computing a forward and inverse discrete wavelet transforms
Assignee: Intel Corp
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Filing: 1998-08-06
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Granted: 1999-11-30
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Expires: 2018-08-06
Abstract
Abstract The invention provides an integrated systolic architecture which can perform both forward and inverse Discrete Wavelet Transforms with a minimum of complexity. A plurality of processing cells, each having an adder and a multiplier, are coupled to a set of multiplexers and delay elements to selectively receive a single input datastream in the forward DWT mode and two datastreams in the inverse DWT mode. In the forward DWT mode, the integrated architecture decomposes the input datastream into two output sequences--a high frequency sub-band output and a low frequency sub-band output. In the inverse DWT mode, the integrated architecture reconstructs the original input sequence by outputting even terms and odd terms on alternating clock cycles. As a result, the architecture can achieve 100% utilization and is suitable to be implemented in VLSI circuitry.
Inventors
- 👤 Tinku Acharya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:42
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
167 words
A single integrated architecture for computing in a first mode a forward Discrete Wavelet Transform and in a second mode an inverse Discrete Wavelet Transform comprising: a set of multiplexers, said multiplexers receiving a first control signal to indicate said first mode and a second control signal to indicate said second mode; a plurality of processing cells, coupled to said multiplexers, to selectively receive a single input sequence in said first mode and two input sequences in said second mode, said cells computing intermediate outputs that are a function of said input sequences and digital filter coefficients; an adder/controller circuit coupled to said processing cells to selectively add said intermediate outputs, said adder/controller generating a high frequency sub-band output sequence and a low frequency sub-band output in said first mode and a reconstructed single output in said second mode; and a plurality of delay elements selectively coupled to said processing cells and said multiplexers, selectively delaying portions of said input sequences to some of said processing cells.
Claim 2
Dependent Claim
167 words
A single integrated architecture for computing in a first mode a forward Discrete Wavelet Transform and in a second mode an inverse Discrete Wavelet Transform comprising: a set of multiplexers, said multiplexers receiving a first control signal to indicate said first mode and a second control signal to indicate said second mode; a plurality of processing cells, coupled to said multiplexers, to selectively receive a single input sequence in said first mode and two input sequences in said second mode, said cells computing intermediate outputs that are a function of said input sequences and digital filter coefficients; an adder/controller circuit coupled to said processing cells to selectively add said intermediate outputs, said adder/controller generating a high frequency sub-band output sequence and a low frequency sub-band output in said first mode and a reconstructed single output in said second mode; and a plurality of delay elements selectively coupled to said processing cells and said multiplexers, selectively delaying portions of said input sequences to some of said processing cells.
Claim 3
Dependent Claim
49 words
An architecture according to claim 1 wherein said reconstructed single output is composed of a first sequence of odd-numbered clock cycle outputs observed on a first output terminal of said adder/controller and a second sequence of even-numbered clock cycle outputs observed on a second output terminal of said adder/controller.
Claim 4
Dependent Claim
45 words
An architecture according to claim 1 wherein said high-frequency sub-band outputs are observed on even clock cycles on a first output terminal of said adder/controller and said low frequency sub-band outputs are observed on odd clock cycles on a second output terminal of said adder/controller.
Claim 5
Dependent Claim
25 words
An architecture according to claim 1 wherein the number of digital filter coefficients is minimized by selecting biorthogonal spline filter coefficients which exhibit symmetric properties.
Claim 6
Independent Claim
85 words
A method for integrating both a forward Discrete Wavelet Transform and inverse Discrete Wavelet Transform in a single architecture comprising the steps of: signaling a first mode to said architecture; computing in said first mode a forward Discrete Wavelet Transform; signaling a second mode to said architecture; and computing in said second mode an inverse Discrete Wavelet Transform, said forward and inverse Discrete Wavelet Transforms performed by a processing cells, a portion of said cells commonly used by said forward and inverse Discrete Wavelet Transforms.
Claim 7
Independent Claim
85 words
A method for integrating both a forward Discrete Wavelet Transform and inverse Discrete Wavelet Transform in a single architecture comprising the steps of: signaling a first mode to said architecture; computing in said first mode a forward Discrete Wavelet Transform; signaling a second mode to said architecture; and computing in said second mode an inverse Discrete Wavelet Transform, said forward and inverse Discrete Wavelet Transforms performed by a processing cells, a portion of said cells commonly used by said forward and inverse Discrete Wavelet Transforms.
Claim 8
Dependent Claim
85 words
A method for integrating both a forward Discrete Wavelet Transform and inverse Discrete Wavelet Transform according to claim 5 wherein the step of signaling a first mode includes the steps of: setting a first control signal low for all clock cycles; setting a second control signal low for all clock cycles; ANDing said second control signal with a clocking signal to generate a third control signal; and selectively providing said first control signal and said third control signal to select multiplexed inputs to said architecture.
Claim 9
Dependent Claim
85 words
A method for integrating both a forward Discrete Wavelet Transform and inverse Discrete Wavelet Transform according to claim 5 wherein the step of signaling a second mode includes the steps of: setting a first control signal high for all clock cycles; setting a second control signal high for all clock cycles; ANDing said second control signal with a clocking signal to generate a third control signal; and selectively providing said first control signal and said third control signal to select multiplexed inputs to said architecture.
Claim 10
Dependent Claim
83 words
A method for integrating both a forward Discrete Wavelet Transform and inverse Discrete Wavelet Transform according to claim 5 wherein the step of computing a forward Discrete Wavelet Transform includes the steps of: utilizing high-pass and low-pass biorthogonal spline filter coefficients in said architecture as a basis for computing said forward Discrete Wavelet Transform; simplifying forward Discrete Wavelet Transform output equations based on symmetry properties in said filter coefficients; and selectively coupling said set of processing cells to compute said simplified output equations.
Claim 11
Dependent Claim
84 words
A method for integrating both a forward Discrete Wavelet Transform and inverse Discrete Wavelet Transform according to claim 5 wherein the step of computing an inverse Discrete Wavelet Transform includes the steps of: utilizing inverse high-pass and low-pass biorthogonal spline filter coefficients in said architectures as a basis for computing said inverse Discrete Wavelet Transform; simplifying inverse Discrete Wavelet Transform output equations based on symmetry properties in said filter coefficients; and selectively coupling said set of processing cells to compute said simplified output equations.
References Cited (Backward Citations)
US5764805A
Cited
US5710835A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |