Patent US5994716A successfully refreshed from Google Patents.
US5994716A
Expired / Lapsed
US
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Integrated circuit and fabricating method and evaluating method of integrated circuit
Assignee: Lapis Semiconductor Co Ltd
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Filing: 1997-05-29
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Granted: 1999-11-30
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Expires: 2017-05-29
Abstract
Abstract A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.
Inventors
- 👤 Masahisa Ikeya
- 👤 Kazuyuki Inokuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:49
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/85; H10P; H10P74/00; H10P74/27; H10P74/277; H10W; H10W20/00; H10W20/20
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
108 words
An integrated circuit comprising: semiconductor chip having active elements on a main face; a substrate having an electrode on a main face; at least two surface electrodes formed on the main face of the semiconductor chip; connection portions including at least two holes respectively formed below the surface electrodes so as to penetrate the semiconductor chip from said main face to a rear face, with said at least two holes being filled with conductive materials; and, an alloyed bonding layer connecting said connection portions together, with said bonding layer being formed between and bonding said rear face of said semiconductor chip and said main face of said substrate.
Claim 2
Dependent Claim
108 words
An integrated circuit comprising: semiconductor chip having active elements on a main face; a substrate having an electrode on a main face; at least two surface electrodes formed on the main face of the semiconductor chip; connection portions including at least two holes respectively formed below the surface electrodes so as to penetrate the semiconductor chip from said main face to a rear face, with said at least two holes being filled with conductive materials; and, an alloyed bonding layer connecting said connection portions together, with said bonding layer being formed between and bonding said rear face of said semiconductor chip and said main face of said substrate.
Claim 3
Dependent Claim
23 words
An integrated circuit according to claim 1, wherein said semiconductor chip has a groove dividing the surface of the rear face into two.
Claim 4
Dependent Claim
46 words
An integrated circuit according to the claim 2, wherein said substrate has a second groove dividing the surface of said main face of said substrate into two, with said second groove being perpendicular to said first groove formed on said rear face of said semiconductor chip.
Claim 5
Dependent Claim
29 words
An integrated circuit according to the claim 1, wherein each of said surface electrodes is provided with an area capable of being touched with at least two external terminals.
Claim 6
Dependent Claim
24 words
An integrated circuit according to the claim 1, wherein said semiconductor chip has a groove dividing the surface of the rear face into four.
Claim 7
Dependent Claim
17 words
An integrated circuit according to the claim 1, wherein said bonding layer is alloyed by solder bonding.
Claim 8
Dependent Claim
17 words
An integrated circuit according to the claim 1, wherein said bonding layer is alloyed by eutectic bonding.
Claim 9
Dependent Claim
16 words
An integrated circuit according to the claim 1, wherein said semiconductor chip consists of a semi-insulator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |