US5989967A
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US
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Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length
Assignee: GlobalFoundries Inc
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Filing: 1998-04-30
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Granted: 1999-11-23
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Expires: 2018-04-30
Abstract
Abstract An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. A mask is formed, from a material resistant to oxidation, upon a conductive gate layer and portions of the conductive gate layer are oxidized to form a gate conductor laterally disposed between a pair of oxide regions. As a result, the gate conductor has an ultra narrow lateral dimension. Source and drain impurity areas are formed self-aligned with sidewall surfaces of the oxide regions. In an embodiment, the oxide regions are removed and lightly doped drain regions are formed self-aligned with sidewall surfaces of the gate conductor. Following LDD formation, the mask is removed, spacers are formed laterally adjacent the gate conductor sidewall surfaces, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas. In an alternative embodiment, following formation of the source and drain impurity areas, the mask is removed and the oxide regions are etched to form sidewall spacers adjacent the gate conductor. Lightly doped drain implant areas are then formed self-aligned to sidewall surfaces of the gate conductor, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas.
Inventors
- 👤 Mark I. Gardner
- 👤 Mark C. Gilmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:06
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01344; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D30/0227; H10D30/0229; H10D64/01304; H10D64/01326; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/693; H10D64/01342
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
99 words
A method for forming a transistor upon and within a semiconductor substrate, comprising: patterning a layer of nitride directly above a layer of silicon-based gate conductor; while maintaining said layer of nitride, oxidizing a portion of the silicon-based gate conductor; removing the oxidized portion of the silicon-based gate conductor; implanting at least a portion of a junction area within the semiconductor substrate having lateral extents aligned with the patterned nitride and the silicon-based gate conductor after said removing step; removing the layer of nitride; and forming metal suicides upon upper surfaces of the gate conductor and the junction area.
Claim 2
Independent Claim
99 words
A method for forming a transistor upon and within a semiconductor substrate, comprising: patterning a layer of nitride directly above a layer of silicon-based gate conductor; while maintaining said layer of nitride, oxidizing a portion of the silicon-based gate conductor; removing the oxidized portion of the silicon-based gate conductor; implanting at least a portion of a junction area within the semiconductor substrate having lateral extents aligned with the patterned nitride and the silicon-based gate conductor after said removing step; removing the layer of nitride; and forming metal suicides upon upper surfaces of the gate conductor and the junction area.
Claim 3
Dependent Claim
26 words
The method as recited in claim 1, wherein said oxidizing comprises exposing said silicon-based gate conductor exclusive of said layer of nitride to an oxygen-bearing ambient.
Claim 4
Dependent Claim
40 words
The method as recited in claim 1, wherein said implanting comprises forwarding a source and drain implant aligned with said patterned nitride after said removing step and before forwarding a lightly doped drain implant aligned with the silicon-based gate conductor.
Claim 5
Independent Claim
130 words
A method for forming a transistor, comprising: providing, in order upon a semiconductor substrate, a first dielectric layer, a second dielectric layer, a conductive gate material, and a masking layer; selectively removing portions of said masking layer and said conductive gate material to form a gate structure, wherein said gate structure comprises a gate layer with a mask configured upon an upper surface of said gate layer; while maintaining said mask, oxidizing portions of said gate layer to form a gate conductor laterally bounded by a pair of oxide regions; introducing impurities into the semiconductor substrate to form source and drain regions; removing the mask from the upper surface of the gate conductor; and forming metal silicides upon upper surfaces of the gate conductor and the source and drain regions.
Claim 6
Independent Claim
130 words
A method for forming a transistor, comprising: providing, in order upon a semiconductor substrate, a first dielectric layer, a second dielectric layer, a conductive gate material, and a masking layer; selectively removing portions of said masking layer and said conductive gate material to form a gate structure, wherein said gate structure comprises a gate layer with a mask configured upon an upper surface of said gate layer; while maintaining said mask, oxidizing portions of said gate layer to form a gate conductor laterally bounded by a pair of oxide regions; introducing impurities into the semiconductor substrate to form source and drain regions; removing the mask from the upper surface of the gate conductor; and forming metal silicides upon upper surfaces of the gate conductor and the source and drain regions.
Claim 7
Dependent Claim
29 words
The method as recited in claim 4, wherein providing said first dielectric layer comprises thermally growing silicon dioxide upon said semiconductor substrate, said semiconductor substrate comprising single crystalline silicon.
Claim 8
Dependent Claim
23 words
The method as recited in claim 4, wherein providing said first dielectric layer comprises chemical vapor depositing silicon dioxide upon said semiconductor substrate.
Claim 9
Dependent Claim
24 words
The method as recited in claim 4, wherein providing said second dielectric layer comprises chemical vapor depositing silicon nitride upon said first dielectric layer.
Claim 10
Dependent Claim
24 words
The method as recited in claim 4, wherein providing said conductive gate layer comprises chemical vapor depositing polycrystalline silicon upon said second dielectric layer.
Claim 11
Dependent Claim
35 words
The method as recited in claim 4, wherein providing said masking layer comprises chemical vapor depositing upon said conductive gate layer a material having a dielectric constant greater than a dielectric constant of silicon dioxide.
Claim 12
Dependent Claim
36 words
The method as recited in claim 4, wherein providing said masking layer comprises chemical vapor depositing upon said conductive gate layer a material having etch characteristics substantially similar to etch characteristics of said second dielectric layer.
Claim 13
Dependent Claim
23 words
The method as recited in claim 4, wherein providing said masking layer comprises chemical vapor depositing silicon nitride upon said conductive gate layer.
Claim 14
Dependent Claim
84 words
The method as recited in claim 4, wherein said introducing impurities comprises: introducing a first impurity distribution at a first impurity concentration into source and drain regions of said semiconductor substrate to form source and drain impurity areas self-aligned with sidewalls of said gate structure; removing said oxide regions; and introducing a second impurity distribution at a second concentration less than said first concentration into said source and drain regions to form lightly doped drain impurity areas self-aligned with sidewalls of said gate conductor.
Claim 15
Dependent Claim
24 words
The method as recited in claim 12, wherein introducing said first impurity distribution comprises ion implanting a first impurity species into said semiconductor substrate.
Claim 16
Dependent Claim
22 words
The method as recited in claim 12, wherein removing said oxide regions comprises isotropically etching said oxide regions using a wet etch.
Claim 17
Dependent Claim
14 words
The method as recited in claim 14, wherein said wet etch comprises hydrogen fluoride.
Claim 18
Dependent Claim
24 words
The method as recited in claim 12, wherein introducing said second impurity distribution comprises ion implanting a second impurity species into said semiconductor substrate.
Claim 19
Dependent Claim
28 words
The method as recited in claim 12, further comprising removing portions of said second dielectric layer from regions of said semiconductor substrate not masked by said gate conductor.
Claim 20
Dependent Claim
22 words
The method as recited in claim 17, wherein said mask and said portions of said second dielectric layer are removed substantially simultaneously.
Claim 21
Dependent Claim
30 words
The method as recited in claim 17, wherein removing said mask and removing said portions of said second dielectric layer comprise anisotropically etching said mask and said second dielectric layer.
Claim 22
Dependent Claim
72 words
The method as recited in claim 4, wherein said introducing impurities comprises: introducing a first impurity distribution at a first impurity concentration into source and drain regions of said semiconductor substrate to form source and drain impurity areas self-aligned with sidewalls of said gate structure; removing portions of said second dielectric layer not masked by said gate structure; and removing portions of said oxide regions to form a pair of sidewall spacers.
Claim 23
Dependent Claim
34 words
The method as recited in claim 20, wherein said mask is removed from above said gate structure substantially simultaneously with removing said portions of said second dielectric layer not masked by said gate structure.
Claim 24
Dependent Claim
43 words
The method as recited in claim 20, further comprising introducing a second impurity distribution at a second concentration less than said first concentration into said source and drain regions to form lightly doped drain impurity areas self-aligned with sidewalls of said gate conductor.
Claim 25
Dependent Claim
30 words
The method as recited in claim 20, wherein removing said mask and removing said portions of said second dielectric layer comprise anisotropically etching said mask and said second dielectric layer.
Claim 26
Dependent Claim
24 words
The method as recited in claim 20, wherein removing portions of said oxide regions comprises isotropically etching said oxide regions using a wet etch.
Claim 27
Dependent Claim
14 words
The method as recited in claim 24, wherein said wet etch comprises hydrogen fluoride.
Claim 28
Independent Claim
115 words
A method for forming a transistor, comprising: forming a mask aligned upon a conductive gate structure, wherein the conductive gate structure is defined a dielectric-spaced distance above a semiconductor substrate; while maintaining said mask, oxidizing portions of said conductive gate structure to form a gate conductor laterally bounded by a pair of oxide regions; implanting impurity ions into said semiconductor substrate to concurrently form source and drain impurity areas self-aligned with sidewall surfaces of said mask and lightly doped drain impurity areas self-aligned with sidewall surfaces of said gate conductor; removing the mask from the gate conductor; and forming metal silicides upon upper surfaces of the gate conductor and the source and drain impurity areas.
Claim 29
Independent Claim
115 words
A method for forming a transistor, comprising: forming a mask aligned upon a conductive gate structure, wherein the conductive gate structure is defined a dielectric-spaced distance above a semiconductor substrate; while maintaining said mask, oxidizing portions of said conductive gate structure to form a gate conductor laterally bounded by a pair of oxide regions; implanting impurity ions into said semiconductor substrate to concurrently form source and drain impurity areas self-aligned with sidewall surfaces of said mask and lightly doped drain impurity areas self-aligned with sidewall surfaces of said gate conductor; removing the mask from the gate conductor; and forming metal silicides upon upper surfaces of the gate conductor and the source and drain impurity areas.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-11-22 | 2003-05-24 | 2003-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-22 | 2007-05-24 | 2007-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-22 | 2011-05-24 | 2011-11-23 | $7700.00 | Window Closed / Lapsed |