US5987587A
Expired / Lapsed
US
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Single chip multiprocessor with shared execution units
Assignee: Google LLC
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Filing: 1997-06-06
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Granted: 1999-11-16
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Expires: 2017-06-06
Abstract
Abstract The present invention relates to multiprocessors which has several microprocessors on a single chip. Efficiency is improved by stripping certain functions that are used less freely from the microprocessor and sharing these functions between several symmetric microprocessors. This method allows each CPU to occupy a smaller area while preserving complete symmetry of capability for software simplification. For example, the shared execution units can include the floating point unit and multimedia execution units.
Inventors
- 👤 David Meltzer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:43
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864; G06F15/7828; G06F15/7832; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
50 words
A multiprocessor chip comprising; (a) a first microprocessor; (b) a second microprocessor, wherein the second microprocessor and the first microprocessor have identical capabilities; (c) a shared execution unit coupled to both the first and second microprocessors; and (d) a shared reservation station coupled to both the first and second microprocessors.
Claim 2
Dependent Claim
50 words
A multiprocessor chip comprising; (a) a first microprocessor; (b) a second microprocessor, wherein the second microprocessor and the first microprocessor have identical capabilities; (c) a shared execution unit coupled to both the first and second microprocessors; and (d) a shared reservation station coupled to both the first and second microprocessors.
Claim 3
Dependent Claim
19 words
The multiprocessor chip of claim 1 wherein said shared execution unit is placed between the first and second microprocessors.
Claim 4
Dependent Claim
16 words
The multiprocessor chip of claim 1 wherein said shared execution unit is a floating point unit.
Claim 5
Dependent Claim
16 words
The multiprocessor chip of claim 1 wherein said shared execution unit is a multimedia execution unit.
Claim 6
Dependent Claim
20 words
The multiprocessor chip of claim 4 wherein both said first and second microprocessors keep a copy of its multimedia registers.
Claim 7
Dependent Claim
17 words
The multiprocessor chip of claim 1 wherein said first and second microprocessors comprise a local register file.
Claim 8
Dependent Claim
39 words
A multiprocessor chip comprising: (a) a first microprocessor; (b) a second microprocessor; (c) a shared execution unit coupled to both the first and second microprocessors; and (d) a shared reservation stack coupled to both the first and second microprocessors.
Claim 9
Dependent Claim
39 words
A multiprocessor chip comprising: (a) a first microprocessor; (b) a second microprocessor; (c) a shared execution unit coupled to both the first and second microprocessors; and (d) a shared reservation stack coupled to both the first and second microprocessors.
Claim 10
Dependent Claim
20 words
The multiprocessor chip of claim 7 wherein said shared reservation stack comprises means to accumulate instructions from an instruction queue.
Claim 11
Dependent Claim
21 words
The multiprocessor chip of claim 7 wherein said shared reservation stack comprises means to accumulate operands from the floating point registers.
Claim 12
Dependent Claim
25 words
The multiprocessor chip of claim 1 further comprises means for steering a result from a shared execution unit to either the first or second microprocessor.
Claim 13
Dependent Claim
60 words
A multiprocessor chip comprising: (a) a first microprocessor; (b) a second microprocessor; (c) a shared execution unit coupled to both the first and second microprocessors; and (d) means for steering a result from a shared execution unit to either the first or second microprocessor, wherein the means for steering includes means for tagging of instructions in a reservation station stack.
Claim 14
Dependent Claim
60 words
A multiprocessor chip comprising: (a) a first microprocessor; (b) a second microprocessor; (c) a shared execution unit coupled to both the first and second microprocessors; and (d) means for steering a result from a shared execution unit to either the first or second microprocessor, wherein the means for steering includes means for tagging of instructions in a reservation station stack.
Claim 15
Dependent Claim
16 words
The multiprocessor chip of claim 7, wherein said shared execution unit is a multimedia execution unit.
Claim 16
Dependent Claim
15 words
The multiprocessor chip of claim 1 wherein said reservation station includes a shared reservation stack.
References Cited (Backward Citations)
US3611307A
Cited
US4152763A
Cited
US4445174A
Cited
US4698753A
Cited
US5117387A
Cited
US5276893A
Cited
US5200564A
Cited
US5428803A
Cited
US5566303A
Cited
US5511212A
Cited
US5685009A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |