Microprogrammed timer processor

Claim 1

A microprogrammed timer processor for servicing each of a plurality of input/output channels at a regularly recurring interval of time while concurrently performing other tasks comprising; storage means for storing a plurality of single instruction programs and a plurality of multiple instruction programs and including address means for accessing the instructions stored in said storage means, clock means defining sequential fetch and execute operations within an instruction cycle, instruction execution means responsive to said clock means for receiving and executing said instructions one at a time and including an instruction register for holding said instructions so that they can be interpreted and acted upon, control means responsive to said clock means for fetching said instructions from said storage means and for interleaving single instruction programs with instructions in said multiple instruction programs so that a single instruction program is executed while an instruction from a multiple instruction program is being fetched, said control means further including time interval setting means for establishing a single instruction execution loop size corresponding to a predetermined number of said single instruction to fix said regularly recurring interval, a table of single instruction pointers addressing said predetermined number of single instruction programs and of entry pointers addressing entry instructions of multiple instruction programs, means including the entry pointers for generating successive multiple instruction pointers, and the control means for interleaving further comprising means for alternately implementing the single instruction pointers and said multiple instruction pointers.