US5987010A
Expired / Lapsed
US
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System and method for providing FDD and TDD modes of operation for a wireless communications device
Assignee: Microsemi Semiconductor US Inc
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Filing: 1997-05-15
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Granted: 1999-11-16
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Expires: 2017-05-15
Abstract
Abstract A system and method is described herein for providing FDD and TDD modes of operation for a wireless communications device. The system includes a clock signal for FDD mode operation, a separate clock signal for TDD mode operation, where the TDD mode clock is twice the frequency of the FDD clock. Additionally, a counter is provided for counting bit times during a transmission or receive frame. The clock counter is reloaded after a pre-specified count is achieved. The pre-specified count is twice as great in TDD mode operation than in FDD mode operation to account for the fact that the bit periods are twice as long in FDD operation than during TDD operation since transmit and receive are at different frequencies and are not sharing the same channel.
Inventors
- 👤 Paul G. Schnizlein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:15
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H03; H03K; H03K5/00; H03K2005/00013; H03K2005/0015; H03K2005/00234; H03K2005/00247
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
128 words
A method of operating in both an FDD mode and a TDD mode for a wireless digital communications device, comprising the steps of: a) providing a first clock signal for FDD mode operation; b) providing a second clock signal for TDD mode operation; c) providing a clock counter; d) selecting between said first clock signal and said second clock signal to be input to said clock counter, wherein for FDD operation said first clock signal is input to said clock counter and for TDD operation said second clock signal is input to said clock counter; and e) reloading said clock counter to a predetermined count value after a pre-specified-count is achieved by said clock counter, the pre-specified count value depending upon one of FDD operation and TDD operation.
Claim 2
Independent Claim
128 words
A method of operating in both an FDD mode and a TDD mode for a wireless digital communications device, comprising the steps of: a) providing a first clock signal for FDD mode operation; b) providing a second clock signal for TDD mode operation; c) providing a clock counter; d) selecting between said first clock signal and said second clock signal to be input to said clock counter, wherein for FDD operation said first clock signal is input to said clock counter and for TDD operation said second clock signal is input to said clock counter; and e) reloading said clock counter to a predetermined count value after a pre-specified-count is achieved by said clock counter, the pre-specified count value depending upon one of FDD operation and TDD operation.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein said clock counter comprises a transmit counter and a receive counter.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein said step of reloading is accomplished after said clock counter achieves a count of 72.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein said step of reloading is accomplished after said clock counter achieves a count of 144.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein said pre-specified count corresponds with a frame rate for a wireless digital communications device.
Claim 7
Dependent Claim
28 words
The method of claim 1, wherein said step of providing a first clock signal is accomplished by selecting between a fixed clock signal and a recovered clock signal.
Claim 8
Dependent Claim
36 words
The method of claim 6, wherein said fixed clock signal and said recovered clock signal are both at a first frequency for FDD mode operation and are both at a second frequency for TDD mode operation.
Claim 9
Dependent Claim
20 words
The method of claim 1, wherein said second clock signal has a rate twice that of said first clock signal.
Claim 10
Dependent Claim
14 words
The method as recited in claim 1 wherein said predetermined count value is zero.
Claim 11
Independent Claim
121 words
A system for implementing FDD and TDD modes of operation for a wireless digital communications device, comprising: a) a first clock signal generator which generates an FDD mode clock signal; b) a second clock signal generator which generates a TDD mode clock signal; c) a clock counter; d) a selector device which selects between an output from said first clock signal generator and said second clock signal generator for input to said clock counter according to whether the system is operating in FDD or TDD mode; wherein said clock counter is reloaded to a predetermined count value after said clock counter achieves a first pre-specified count for FDD mode of operations, and a second pre-specified count for TDD mode of operation.
Claim 12
Independent Claim
121 words
A system for implementing FDD and TDD modes of operation for a wireless digital communications device, comprising: a) a first clock signal generator which generates an FDD mode clock signal; b) a second clock signal generator which generates a TDD mode clock signal; c) a clock counter; d) a selector device which selects between an output from said first clock signal generator and said second clock signal generator for input to said clock counter according to whether the system is operating in FDD or TDD mode; wherein said clock counter is reloaded to a predetermined count value after said clock counter achieves a first pre-specified count for FDD mode of operations, and a second pre-specified count for TDD mode of operation.
Claim 13
Dependent Claim
23 words
The system of claim 10, wherein said FDD mode clock signal has a rate one half that of said TDD mode clock signal.
Claim 14
Dependent Claim
18 words
The system of claim 10, wherein said second pre-specified count is twice that of said first pre-specified count.
Claim 15
Dependent Claim
25 words
The system of claim 10, wherein said first count and said second count each correspond to a frame rate for a wireless digital communications device.
Claim 16
Dependent Claim
17 words
The system of claim 10, wherein said clock counter comprises a transmit counter and a receive counter.
Claim 17
Dependent Claim
29 words
The system of claim 10, wherein said first clock signal generator generates said FDD mode clock signal by selecting between a fixed clock signal and a recovered clock signal.
Claim 18
Dependent Claim
29 words
The system of claim 10, wherein said second clock signal generator generates said TDD mode clock signal by selecting between a fixed clock signal and a recovered clock signal.
Claim 19
Dependent Claim
14 words
The system as recited in claim 10 wherein said predetermined count value is zero.
Claim 20
Independent Claim
168 words
A system for implementing FDD and TDD modes of operation for a wireless digital communications device, comprising: a base clock signal generator; a first division circuit coupled to the base clock signal generator, the first division circuit operable to generate an FDD clock signal from a base clock signal generated by the base clock signal generator; a second division circuit coupled to the base clock signal generator, the second division circuit operable to generate a TDD clock signal from the base clock signal; a selector coupled to the first and second division circuits, the selector operable to receive a mode select signal, the selector selecting between the FDD clock signal and the TDD clock signal according to the mode select signal; a counter coupled to the selector; and a decode circuit coupled to the counter, the decode circuit operable to receive a counter signal from the counter and to provide a reload signal to the counter, the reload signal causing the counter to return to a predetermined value.
Claim 21
Independent Claim
168 words
A system for implementing FDD and TDD modes of operation for a wireless digital communications device, comprising: a base clock signal generator; a first division circuit coupled to the base clock signal generator, the first division circuit operable to generate an FDD clock signal from a base clock signal generated by the base clock signal generator; a second division circuit coupled to the base clock signal generator, the second division circuit operable to generate a TDD clock signal from the base clock signal; a selector coupled to the first and second division circuits, the selector operable to receive a mode select signal, the selector selecting between the FDD clock signal and the TDD clock signal according to the mode select signal; a counter coupled to the selector; and a decode circuit coupled to the counter, the decode circuit operable to receive a counter signal from the counter and to provide a reload signal to the counter, the reload signal causing the counter to return to a predetermined value.
Claim 22
Dependent Claim
30 words
The system of claim 18 wherein the decode circuit is operable to receive the mode select signal, the decode circuit providing the reload signal according to the mode select signal.
Claim 23
Dependent Claim
32 words
The system of claim 18 wherein the decode circuit is operable to receive a clock signal selected by the selector, the decode circuit providing the reload signal according to the clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |