Semiconductor memory device having internal voltage down-converting circuit reducing current consumption upon power ON

Claim 2

A semiconductor memory device comprising: an internal voltage down-converting circuit activated in response to activation of a voltage down-converting activation signal for down-converting an external power supply voltage to produce an internal power supply voltage; a power-on detector circuit for generating a power-on detection signal entering an active state in response to a start of application of said external power supply voltage; and control means for forcibly maintaining said voltage down-converting activation signal in an inactive state in response to activation of said power-on detection signal.

Claim 3

The semiconductor memory device in accordance with claim 1, further comprising delay means for delaying said power-on detection signal by a prescribed time for supplying to said control means, said control means including means for stopping maintenance of said voltage down-converting activation signal in said inactive state in response to an inactive state of an output signal from said delay means.

Claim 4

A semiconductor memory device comprising: an internal voltage down-converting circuit activated in response to activation of a voltage down-converting activation signal for down-converting an external power supply voltage to produce an internal power supply voltage; a power-on detector circuit for generating a power-on detection signal entering an active state in response to a start of application of said external power supply voltage; and control means for maintaining said voltage down-converting activation signal in an inactive state in response to activation of said power-on detection signal, wherein said control means comprises: dummy cycle detector means for detecting instruction of a dummy cycle for resetting an internal circuit into an initial state in response to an operation cycle instruction signal, and stop means for stopping an operation of maintaining said voltage down-converting activation signal in said inactive state in response to activation of a dummy cycle detection instruction signal from said dummy cycle detector means.

Claim 5

A semiconductor memory device comprising: an internal voltage down-converting circuit activated in response to activation of a voltage down-converting activation signal for down-converting an external power supply voltage to produce an internal power supply voltage; a power-on detector circuit for generating a power-on detection signal entering an active state in response to a start of application of said external power supply voltage; and control means for maintaining said voltage down-converting activation signal in an inactive state in response to activation of said power-on detection signal, wherein said control means comprises: dummy cycle detector means for detecting instruction of a dummy cycle for resetting an internal circuit into an initial state in response to an operation cycle instruction signal, and stop means for stopping an operation of maintaining said voltage down-converting activation signal in said inactive state in response to activation of a dummy cycle detection instruction signal from said dummy cycle detector means.

Claim 6

The semiconductor memory device in accordance with claim 3, wherein said control means further comprises active control signal generator means for generating an active control signal for activating said internal voltage down-converting circuit in accordance with said operation cycle instruction signal, the stop means included in said control means including a gate circuit for generating said voltage down-converting activation signal in accordance with said active control signal in response to activation of said dummy cycle detection instruction signal.

Claim 7

A semiconductor memory device comprising: an internal voltage down-converting circuit activated in response to activation of a voltage down-converting activation signal for down-converting an external power supply voltage to produce an internal power supply voltage; internal operation activation signal generator means for generating an internal operation activation signal for activating said voltage down-converting activation signal in response to an external operation cycle defining signal; a power-on detector circuit for generating a power-on detection signal entering an active state in response to start of application of said external power supply voltage; dummy cycle detector means for detecting an instruction of a dummy cycle for resetting an internal circuit into an initial state in response to said power-on detection signal and said operation cycle defining signal and generating a dummy cycle detection signal activated in the detection of the dummy cycle instruction; and control means for receiving said dummy cycle detection signal to stop generation of said voltage down-converting activation signal in accordance with said internal operation activation signal and to maintain said voltage down-converting activation signal in an inactive state until activation of said dummy cycle detection signal.

Claim 8

A semiconductor memory device comprising: an internal voltage down-converting circuit activated in response to activation of a voltage down-converting activation signal for down-converting an external power supply voltage to produce an internal power supply voltage; internal operation activation signal generator means for generating an internal operation activation signal for activating said voltage down-converting activation signal in response to an external operation cycle defining signal; a power-on detector circuit for generating a power-on detection signal entering an active state in response to start of application of said external power supply voltage; dummy cycle detector means for detecting an instruction of a dummy cycle for resetting an internal circuit into an initial state in response to said power-on detection signal and said operation cycle defining signal and generating a dummy cycle detection signal activated in the detection of the dummy cycle instruction; and control means for receiving said dummy cycle detection signal to stop generation of said voltage down-converting activation signal in accordance with said internal operation activation signal and to maintain said voltage down-converting activation signal in an inactive state until activation of said dummy cycle detection signal.

Claim 9

The semiconductor memory device in accordance with claim 5, further comprising a delay circuit for delaying said power-on detection signal by a prescribed time for supplying to said control means.

Claim 10

The semiconductor memory device in accordance with claim 6, wherein said control means includes means for carrying out operations of stopping generation of said voltage down-converting activation signal in accordance with said internal operation activation signal and for maintaining said voltage down-converting activation signal in an said inactive state in response to an active state of an output signal from said delay circuit and an inactive state of said dummy cycle detection signal.