US5986948A
Expired / Lapsed
US
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Data communication for memory
Assignee: Round Rock Research LLC
•
Filing: 1998-09-23
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Granted: 1999-11-16
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Expires: 2018-09-23
Abstract
Abstract A memory circuit is described which has an output data strobe signal that indicates when valid data is available on the output lines. Several alternate signals and circuits are described which can be used for the output strobe signal. An echo clock signal is described which selectively follows an input clock signal in a synchronous memory system and indicated when valid output data is available. The output strobe signal is used to speed the reading of data from the output line by allowing a microprocessor, or other external circuit, to read the data from the output lines as soon as it is valid, thereby eliminating the need to wait a specified period of time.
Inventors
- 👤 Eugene H. Cloud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1051; G11C7/1063; G11C11/4076; G11C7/22
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
96 words
A memory module comprising: a plurality of synchronous memories; a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module, and an output driver circuit adapted to receive the pulsed signal and provide an output data strobe signal indicating when valid data is available from the memory module on data communication lines.
Claim 2
Dependent Claim
96 words
A memory module comprising: a plurality of synchronous memories; a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module, and an output driver circuit adapted to receive the pulsed signal and provide an output data strobe signal indicating when valid data is available from the memory module on data communication lines.
Claim 3
Dependent Claim
27 words
The memory module of claim 1 wherein the output data strobe signal is synchronized with the start of the output data from the integrated circuit memory device.
Claim 4
Dependent Claim
18 words
The memory module of claim 2 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 5
Dependent Claim
43 words
The memory module of claim 1 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.
Claim 6
Dependent Claim
18 words
The memory module of claim 4 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 7
Dependent Claim
25 words
The memory module of claim 1 wherein the output data strobe signal has a frequency which is n-times a frequency of the clock input signal.
Claim 8
Dependent Claim
18 words
The memory module of claim 6 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 9
Dependent Claim
43 words
The memory module of claim 6 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.
Claim 10
Dependent Claim
25 words
The memory module of claim 6 wherein the output data strobe signal has a frequency which is two-times a frequency of the clock input signal.
Claim 11
Dependent Claim
33 words
The memory module of claim 6 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.
Claim 12
Dependent Claim
18 words
The memory module of claim 6 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 13
Dependent Claim
33 words
The memory module of claim 1 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.
Claim 14
Dependent Claim
18 words
The memory module of claim 1 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 15
Dependent Claim
114 words
A memory module comprising: a plurality of synchronous memories; a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module; and an output driver circuit adapted to receive the pulsed signal and provide a plurality of output data strobe signals indicating when valid data is available from the memory module on data communication lines, each one of the plurality of output data strobe signals corresponding with a byte of data.
Claim 16
Dependent Claim
114 words
A memory module comprising: a plurality of synchronous memories; a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module; and an output driver circuit adapted to receive the pulsed signal and provide a plurality of output data strobe signals indicating when valid data is available from the memory module on data communication lines, each one of the plurality of output data strobe signals corresponding with a byte of data.
Claim 17
Dependent Claim
27 words
The memory module of claim 14 wherein the output data strobe signal is synchronized with the start of the output data from the integrated circuit memory device.
Claim 18
Dependent Claim
18 words
The memory module of claim 15 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 19
Dependent Claim
43 words
The memory module of claim 14 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.
Claim 20
Dependent Claim
18 words
The memory module of claim 17 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 21
Dependent Claim
25 words
The memory module of claim 14 wherein the output data strobe signal has a frequency which is n-times a frequency of the clock input signal.
Claim 22
Dependent Claim
18 words
The memory module of claim 19 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 23
Dependent Claim
43 words
The memory module of claim 19 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.
Claim 24
Dependent Claim
25 words
The memory module of claim 19 wherein the output data strobe signal has a frequency which is two-times a frequency of the clock input signal.
Claim 25
Dependent Claim
33 words
The memory module of claim 19 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.
Claim 26
Dependent Claim
18 words
The memory module of claim 19 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 27
Dependent Claim
33 words
The memory module of claim 14 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.
Claim 28
Dependent Claim
18 words
The memory module of claim 14 wherein the output data strobe signal is inhibited during non-read memory operations.
Claim 29
Dependent Claim
75 words
A synchronous memory device comprising: an input for receiving a clock signal; an output for providing a plurality of echo clock signals which substantially follows the clock signal during a data read operation, transitions of the echo clock signal indicate when data is available on data output lines, each one of the plurality of the echo clock signals corresponding with a byte of output data; and a generating circuit for producing the echo clock signals.
Claim 30
Dependent Claim
75 words
A synchronous memory device comprising: an input for receiving a clock signal; an output for providing a plurality of echo clock signals which substantially follows the clock signal during a data read operation, transitions of the echo clock signal indicate when data is available on data output lines, each one of the plurality of the echo clock signals corresponding with a byte of output data; and a generating circuit for producing the echo clock signals.
Claim 31
Dependent Claim
22 words
The synchronous memory device of claim 27 wherein the echo clock signals also substantially follow the clock signal during non-data read operations.
Claim 32
Dependent Claim
29 words
The synchronous memory device of claim 27 wherein either a rising or falling transition of the echo clock signals indicate that data is available on the data output lines.
Claim 33
Dependent Claim
23 words
The synchronous memory device of claim 27 wherein the echo clock signals indicate a start of data transmission on the data output lines.
Claim 34
Independent Claim
68 words
A method of outputting data from a synchronous memory device, the method comprising: receiving a clock input signal with the synchronous memory device; initiating a memory read operation; generating an echo clock signal which substantially follows the clock signal during the memory read operation; and outputting the echo clock signal from the synchronous memory data, the echo clock signal corresponds to output data from the synchronous memory device.
Claim 35
Independent Claim
68 words
A method of outputting data from a synchronous memory device, the method comprising: receiving a clock input signal with the synchronous memory device; initiating a memory read operation; generating an echo clock signal which substantially follows the clock signal during the memory read operation; and outputting the echo clock signal from the synchronous memory data, the echo clock signal corresponds to output data from the synchronous memory device.
Claim 36
Dependent Claim
37 words
The method of claim 31, wherein the echo clock signal is synchronized with data output from the synchronous memory device so that a transition of the echo clock signal corresponds to a start of the data output.
Claim 37
Dependent Claim
24 words
The method of claim 31 wherein a transition of the echo clock is ninety (90) degrees out-of-phase with a start of the data output.
Claim 38
Dependent Claim
18 words
The method of claim 31 wherein the output of the echo clock signal is inhibited during non-read operations.
Claim 39
Dependent Claim
26 words
The method of claim 31 wherein both rising and falling transitions of the echo clock signal are synchronized with data output from the synchronous memory device.
Claim 40
Independent Claim
76 words
A method of outputting data from a synchronous memory device, the method comprising: receiving a clock input signal with the synchronous memory device; initiating a memory read operation; generating a plurality of echo clock signals which substantially follows the clock signal during the memory read operation; and outputting the echo clock signals from the synchronous memory data, each one of the echo clock signals correspond to a byte of output data from the synchronous memory device.
Claim 41
Independent Claim
76 words
A method of outputting data from a synchronous memory device, the method comprising: receiving a clock input signal with the synchronous memory device; initiating a memory read operation; generating a plurality of echo clock signals which substantially follows the clock signal during the memory read operation; and outputting the echo clock signals from the synchronous memory data, each one of the echo clock signals correspond to a byte of output data from the synchronous memory device.
Claim 42
Dependent Claim
37 words
The method of claim 36 wherein the echo clock signals are synchronized with data output from the synchronous memory device so that a transition of the echo clock signals correspond to a start of the data output.
Claim 43
Dependent Claim
25 words
The method of claim 36 wherein a transition of the echo clock signals are ninety (90) degrees out-of-phase with a start of the data output.
Claim 44
Dependent Claim
18 words
The method of claim 36 wherein the output of the echo clock signals are inhibited during non-read operations.
Claim 45
Dependent Claim
26 words
The method of claim 36 wherein both rising and falling transitions of the echo clock signals are synchronized with data output from the synchronous memory device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |