US5985748A
Expired / Lapsed
US
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Method of making a semiconductor device using chemical-mechanical polishing having a combination-step process
Assignee: Apple Inc
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Filing: 1997-12-01
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Granted: 1999-11-16
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Expires: 2017-12-01
Abstract
Abstract A method of chemical-mechanical polishing of a semiconductor device utilizes a combination of polishing steps, including a first step using a first slurry containing an abrasive component (i.e., mechanical component) and a chemical component (i.e., chemical reactants), and a second polishing step using a second slurry having a reduced amount of the abrasive component. The method is carried out with respect to metal (39), such as copper, deposited on a dielectric layer (34) and the first polishing step is stopped before the entirety of the metal overlying the dielectric layer is removed. In one embodiment, the second slurry has no abrasive component.
Inventors
- 👤 David K. Watts
- 👤 Franklin D. Nkansah
- 👤 John Mendonca
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:26
CPC Classifications
H; H10; H10P; H10P52/00; H10P52/40; H10P52/403; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
107 words
A method of making a semiconductor device, comprising the steps of: forming a dielectric layer over a substrate; etching openings in the dielectric layer; filling the openings and overlying the dielectric layer with a metal; using chemical-mechanical polishing to remove a first portion of the metal overlying the dielectric layer using a first slurry containing a first proportion of an abrasive component, thereby leaving a second portion of the metal, which overlies the dielectric layer; and using chemical-mechanical polishing to remove the second portion of the metal using a second slurry containing a second proportion of abrasive component, said second proportion being less than said first proportion.
Claim 2
Independent Claim
107 words
A method of making a semiconductor device, comprising the steps of: forming a dielectric layer over a substrate; etching openings in the dielectric layer; filling the openings and overlying the dielectric layer with a metal; using chemical-mechanical polishing to remove a first portion of the metal overlying the dielectric layer using a first slurry containing a first proportion of an abrasive component, thereby leaving a second portion of the metal, which overlies the dielectric layer; and using chemical-mechanical polishing to remove the second portion of the metal using a second slurry containing a second proportion of abrasive component, said second proportion being less than said first proportion.
Claim 3
Dependent Claim
23 words
The method of claim 1, wherein the dielectric layer is selected from a group consisting of silicon dioxide, silicon nitride, and organic polymers.
Claim 4
Dependent Claim
13 words
The method of claim 2, wherein the dielectric layer is fluorinated silicon dioxide.
Claim 5
Dependent Claim
27 words
The method of claim 1, wherein at least one of the first slurry and the second slurry further comprises a chemical component that reacts with the metal.
Claim 6
Dependent Claim
16 words
The method of claim 4, wherein the chemical component comprises ammonium citrate, 1,2,4-triazole, and hydrogen peroxide.
Claim 7
Dependent Claim
11 words
The method of claim 1, wherein the abrasive component is alumina.
Claim 8
Dependent Claim
18 words
The method of claim 1, wherein the second proportion of abrasive component is less than 1% by weight.
Claim 9
Dependent Claim
19 words
The method of claim 1, wherein the first proportion of abrasive component is approximately 2 to 15% by weight.
Claim 10
Dependent Claim
15 words
The method of claim 1, wherein the metal is selected from aluminum, copper, and tungsten.
Claim 11
Dependent Claim
39 words
The method of claim 1, wherein etching openings in the dielectric layer comprises the steps of: etching trenches in the dielectric layer; and etching via holes through the dielectric layer, wherein the via holes are contiguous with respective trenches.
Claim 12
Independent Claim
98 words
A method of making a semiconductor device, comprising the steps of: forming a dielectric layer over a substrate; etching openings in the dielectric layer; filling the openings and overlying the dielectric layer with a metal; and chemical-mechanical polishing the metal overlying the dielectric layer using a slurry containing a chemical component that reacts with the metal, and a material which has a propensity to remove the dielectric layer and, after removing a first portion of the metal overlying the dielectric layer and before removing all of the metal overlying the dielectric layer, reducing a content of said material.
Claim 13
Independent Claim
98 words
A method of making a semiconductor device, comprising the steps of: forming a dielectric layer over a substrate; etching openings in the dielectric layer; filling the openings and overlying the dielectric layer with a metal; and chemical-mechanical polishing the metal overlying the dielectric layer using a slurry containing a chemical component that reacts with the metal, and a material which has a propensity to remove the dielectric layer and, after removing a first portion of the metal overlying the dielectric layer and before removing all of the metal overlying the dielectric layer, reducing a content of said material.
Claim 14
Dependent Claim
12 words
The method of claim 11, wherein said material comprises an abrasive component.
Claim 15
Dependent Claim
24 words
The method of claim 11, wherein reducing the content of said material lowers the content of said material to less than 1% by weight.
Claim 16
Dependent Claim
21 words
The method of claim 13, wherein reducing the content of said material lowers the content of said material to substantially zero.
Claim 17
Dependent Claim
10 words
The method of claim 11, wherein said material comprises alumina.
Claim 18
Dependent Claim
39 words
The method of claim 11, wherein etching openings in the dielectric layer comprises the steps of: etching trenches in the dielectric layer; and etching via holes in the dielectric layer, wherein the via holes are contiguous with respective trenches.
Claim 19
Independent Claim
88 words
A method of chemical-mechanical polishing a semiconductor wafer, comprising the steps of: polishing a metal layer on a semiconductor wafer using a first slurry containing a chemical component and a first proportion of an abrasive component; and substituting a second slurry for the first slurry after a first portion of the metal layer, less than an entirety of the metal layer, has been removed, said second slurry containing a chemical component and a second proportion of an abrasive component, said second proportion being less than said first proportion.
Claim 20
Independent Claim
88 words
A method of chemical-mechanical polishing a semiconductor wafer, comprising the steps of: polishing a metal layer on a semiconductor wafer using a first slurry containing a chemical component and a first proportion of an abrasive component; and substituting a second slurry for the first slurry after a first portion of the metal layer, less than an entirety of the metal layer, has been removed, said second slurry containing a chemical component and a second proportion of an abrasive component, said second proportion being less than said first proportion.
Claim 21
Dependent Claim
16 words
The method of claim 17, wherein the second proportion is approximately zero to 1% by weight.
Claim 22
Dependent Claim
16 words
The method of claim 17, wherein the first proportion is approximately 2 to 15% by weight.
Claim 23
Dependent Claim
23 words
The method of claim 17, wherein the abrasive component of the first slurry and the abrasive component of the second slurry comprises alumina.
Claim 24
Independent Claim
159 words
A method of making vias and interconnects in a semiconductor device, comprising the steps of: forming a dielectric layer over a substrate; etching trenches partially through the dielectric layer; etching via holes in the dielectric layer, wherein the via holes are contiguous with the trenches; filling the via holes and trenches, and overlying the dielectric layer with a metal, whereby vias are formed in the via holes and interconnects are formed in the trenches; chemical-mechanical polishing to remove a first portion of the metal overlying the dielectric layer using a first slurry comprising a chemical component and an abrasive component; and after removing the first portion of the metal overlying the dielectric layer and before removing all of the metal over the dielectric layer, chemical-mechanical polishing using a second slurry containing chemical component and a reduced proportion of the abrasive component until the metal overlying the dielectric layer has been substantially removed, thereby leaving behind the vias and interconnects.
Claim 25
Independent Claim
159 words
A method of making vias and interconnects in a semiconductor device, comprising the steps of: forming a dielectric layer over a substrate; etching trenches partially through the dielectric layer; etching via holes in the dielectric layer, wherein the via holes are contiguous with the trenches; filling the via holes and trenches, and overlying the dielectric layer with a metal, whereby vias are formed in the via holes and interconnects are formed in the trenches; chemical-mechanical polishing to remove a first portion of the metal overlying the dielectric layer using a first slurry comprising a chemical component and an abrasive component; and after removing the first portion of the metal overlying the dielectric layer and before removing all of the metal over the dielectric layer, chemical-mechanical polishing using a second slurry containing chemical component and a reduced proportion of the abrasive component until the metal overlying the dielectric layer has been substantially removed, thereby leaving behind the vias and interconnects.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |