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US5982837A
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Automatic baud rate detector
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-06-16
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Granted: 1999-11-09
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Expires: 2017-06-16
Abstract
Abstract An automatic baud rate detector circuit includes a serial input, a counter, a register, a comparator and a state machine circuit. The serial input receives a serial data stream having a bit defined by a first transition from a first logic state to a second logic state and next subsequent second transition from the second logic state to the first logic state. A counter increments a sample count in response to a clock signal when a count enable signal supplied to the counter is active. A register coupled to the counter stores the sample count as a minimum count when a load control signal supplied to the counter is active. The comparator is coupled to the counter and the register and generates a compare signal which indicates whether the sample count is less than the minimum count. The state machine circuit is coupled to the serial input for receiving the serial data stream and supplies the count enable signal to the counter and the load enable signal to the register. The state machine circuit activates the count enable signal from the first transition to the second transition in the serial data stream and activates the load enable signal when the first compare signal indicates the sample count is less than the minimum count. After one or more cycles of the state machine circuit, the minimum count stored in the register can be used to calculate the baud rate of the serial data stream.
Inventors
- 👤 Tim Earnest
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:47
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0262
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
227 words
An automatic baud rate detector circuit comprising: a serial input for receiving a serial data stream having a bit defined by a first transition from a first logic state to a second logic state and a second transition, which is the next subsequent transition, from the second logic state to the first logic state; a counter which increments a sample count in response to a clock signal when a count enable signal supplied to the counter is active; a register coupled to the counter, which stores the sample count as a minimum count when a load enable signal supplied to the counter is active, wherein the minimum count is representative of a baud rate of the serial data stream; a first comparator coupled to the counter and the register and generating a first compare signal which indicates whether the sample count is less than the minimum count; and a state machine circuit which is coupled to the serial input for receiving the serial data stream and which supplies the count enable signal to the counter and the load enable signal to the register, wherein the state machine circuit activates the count enable signal from the first transition to the second transition in the serial data stream and activates the load enable signal when the first compare signal indicates the sample count is less than the minimum count.
Claim 2
Dependent Claim
227 words
An automatic baud rate detector circuit comprising: a serial input for receiving a serial data stream having a bit defined by a first transition from a first logic state to a second logic state and a second transition, which is the next subsequent transition, from the second logic state to the first logic state; a counter which increments a sample count in response to a clock signal when a count enable signal supplied to the counter is active; a register coupled to the counter, which stores the sample count as a minimum count when a load enable signal supplied to the counter is active, wherein the minimum count is representative of a baud rate of the serial data stream; a first comparator coupled to the counter and the register and generating a first compare signal which indicates whether the sample count is less than the minimum count; and a state machine circuit which is coupled to the serial input for receiving the serial data stream and which supplies the count enable signal to the counter and the load enable signal to the register, wherein the state machine circuit activates the count enable signal from the first transition to the second transition in the serial data stream and activates the load enable signal when the first compare signal indicates the sample count is less than the minimum count.
Claim 3
Dependent Claim
148 words
The automatic baud rate detector circuit of claim 1 wherein the state machine circuit comprises a synchronous logic circuit having a sequence of states, including a) supplying a counter reset signal to the counter that initializes the sample count, b) waiting for the first transition from the first logic state to the second logic state, c) activating the count enable signal when the first transition is detected, d) waiting for the second transition from the second logic state to the first logic state, e) deactivating the count enable signal when the second transition is detected, f) receiving the first compare signal from the first comparator, and g) activating the load enable signal if the first compare signal indicates the sample count is less than the minimum count, and wherein the state machine circuit then returns to the state of a) supplying the counter reset signal to the counter.
Claim 4
Dependent Claim
78 words
The automatic baud rate detector circuit of claim 1 wherein the state machine circuit maintains a count valid flag, receives a detector reset signal and resets the count enable flag upon receipt of the detector reset signal, and wherein the state machine circuit activates the load enable signal if the sample count is less than the minimum count or if the count valid flag is reset and sets the count valid flag after activating the load enable signal.
Claim 5
Dependent Claim
51 words
The automatic baud rate detector circuit of claim 1 wherein the counter generates a carry signal which is active when the counter overflows, and wherein the state machine circuit activates the load enable signal only if the sample count is less than the minimum count and the carry signal is inactive.
Claim 6
Dependent Claim
84 words
The automatic baud rate detector circuit of claim 1 and further comprising a second comparator coupled to the counter, which compares the sample count to a predetermined constant and supplies a second compare signal to the state machine which indicates whether the sample count is at least as great as the predetermined constant, and wherein state machine circuit activates the load enable signal only if the sample count is less than the minimum count and is at least as great as the predetermined constant.
Claim 7
Dependent Claim
27 words
The automatic baud rate detector circuit of claim 5 wherein the predetermined constant corresponds to a baud rate that is greater than a maximum allowable baud rate.
Claim 8
Independent Claim
105 words
A method of detecting baud rate, the method comprising: receiving a serial data stream having a bit defined by a first transition from a first logic state to a second logic state and a second transition, which is the next subsequent transition, from the second logic state to the first logic state; receiving a clock signal having a plurality of cycles, each cycle having a clock period; counting a number of the clock cycles received between the first transition and the second transition; and calculating a baud rate of the serial data stream based on the number of counted clock cycles and the clock period.
Claim 9
Independent Claim
105 words
A method of detecting baud rate, the method comprising: receiving a serial data stream having a bit defined by a first transition from a first logic state to a second logic state and a second transition, which is the next subsequent transition, from the second logic state to the first logic state; receiving a clock signal having a plurality of cycles, each cycle having a clock period; counting a number of the clock cycles received between the first transition and the second transition; and calculating a baud rate of the serial data stream based on the number of counted clock cycles and the clock period.
Claim 10
Dependent Claim
109 words
The method of claim 7 wherein the step of counting comprises: maintaining a minimum count; initializing a counter, wherein the counter increments a sample count in response to the clock signal when the counter is enabled; detecting the first transition; enabling the counter after detecting the first transition; detecting the second transition; reading the sample count from the counter after detecting the second transition; comparing the sample count with the minimum count; replacing the minimum count with the sample count if the sample count is less than the minimum count; and repeating the steps of initializing, detecting the first transition, enabling, detecting the second transition, reading, comparing and replacing.
Claim 11
Dependent Claim
82 words
The method of claim 8 wherein the step of counting further comprises: receiving a reset signal having an active state and an inactive state; maintaining a count valid flag; resetting the count valid flag when the reset signal is active; replacing the minimum count with the sample count if the sample count is less than the minimum count or if the count valid flag is reset; and setting the count valid flag when the minimum count is replaced with the sample count.
Claim 12
Dependent Claim
53 words
The method of claim 8 wherein the counter generates a carry signal which is active when the sample count overflows and wherein the step of counting further comprises: replacing the minimum count with the sample count only if the sample count is less than the minimum count and the carry signal is inactive.
Claim 13
Dependent Claim
50 words
The method of claim 8 wherein the step of counting further comprises: comparing the sample count with a predetermined constant; and replacing the minimum count with the sample count only if the sample count is less than the minimum count and is at least as great as the predetermined constant.
Claim 14
Dependent Claim
41 words
The method of claim 11 wherein the step of comparing the sample count with a predetermined constant comprises comparing the sample count to a predetermined constant which corresponds to a baud rate that is greater than a maximum allowable baud rate.
Claim 15
Dependent Claim
61 words
The method of claim 8 wherein: the step of detecting the first transition comprises detecting a transition in the serial data stream from a logic high state to a logic low state; and the step of detecting the second transition comprises detecting the next subsequent transition in the serial data stream from the logic low state to the logic low state.
Claim 16
Dependent Claim
46 words
The method of claim 7 and further comprising: maintaining a table of predetermined baud rates; comparing the calculated baud rate with the predetermined baud rates; and providing a baud rate output which corresponds to the predetermined baud rate that is closest to the calculated baud rate.
Claim 17
Dependent Claim
79 words
The method of claim 7 wherein: the step of receiving comprises receiving a plurality of bits; the step of counting comprises counting a number of the clock cycles received between the first transition and the second transition for each of the plurality of bits and selecting a lowest of the numbers of counted clock cycles for the plurality of bits; and the step of calculating comprises calculating the baud rate based on the lowest number of counted clock cycles.
Claim 18
Dependent Claim
218 words
An integrated circuit comprising: an internal bus; a serial port for receiving a serial data stream having a bit defined by a first transition from a logic high state to a logic low state and a second transition, which is the next subsequent transition, from the logic low state to the logic high state; a host processor coupled to the internal transfer bus; a clock generator which generates a clock signal; a synchronous serial communications controller coupled to the clock generator and between the internal bus and the serial interface port, the controller comprising: means for detecting the first transition, activating a count enable signal after detecting the first transition, detecting the second transition and then deactivating the count enable signal after detecting the second transition; means for incrementing a sample count based on the clock signal when the count enable signal is active; means for storing a minimum count which is readable by the host processor over the internal bus; means for comparing the sample count with the minimum count; and means for replacing the minimum count with the sample count if the sample count is less than the minimum count; and wherein the host processor comprises means for calculating a baud rate of the serial data stream based on the minimum count and the clock signal.
Claim 19
Dependent Claim
218 words
An integrated circuit comprising: an internal bus; a serial port for receiving a serial data stream having a bit defined by a first transition from a logic high state to a logic low state and a second transition, which is the next subsequent transition, from the logic low state to the logic high state; a host processor coupled to the internal transfer bus; a clock generator which generates a clock signal; a synchronous serial communications controller coupled to the clock generator and between the internal bus and the serial interface port, the controller comprising: means for detecting the first transition, activating a count enable signal after detecting the first transition, detecting the second transition and then deactivating the count enable signal after detecting the second transition; means for incrementing a sample count based on the clock signal when the count enable signal is active; means for storing a minimum count which is readable by the host processor over the internal bus; means for comparing the sample count with the minimum count; and means for replacing the minimum count with the sample count if the sample count is less than the minimum count; and wherein the host processor comprises means for calculating a baud rate of the serial data stream based on the minimum count and the clock signal.
Claim 20
Dependent Claim
15 words
The integrated circuit of claim 16 wherein the controller comprises a Universal Asynchronous Receiver/Transmitter (UART).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |