US5982683A
Expired / Lapsed
US
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Enhanced method of testing semiconductor devices having nonvolatile elements
Assignee: Lattice Semiconductor Corp
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Filing: 1998-03-23
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Granted: 1999-11-09
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Expires: 2018-03-23
Abstract
Abstract An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.
Inventors
- 👤 James A. Watson
- 👤 Fabiano Fontana
- 👤 Jenny Chui
- 👤 Steve Choi
- 👤 Benjamin Lau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
219 words
A method of testing regions of a semiconductor device having nonvolatile memory elements in control circuits wherein the control circuits control the state of elements in the semiconductor device, the method comprising: determining the probability of defects occurring in each region of the semiconductor device having nonvolatile memory elements in control circuits; placing the nonvolatile memory elements in a high impedance state; selecting a first region of the semiconductor device having the highest probability of containing a defect; activating bypass circuitry in the first region of the semiconductor device to bypass a number of nonvolatile memory elements in the first selected region and applying test vectors to the elements controlled by the number of bypassed nonvolatile memory elements; activating bypass circuitry in the first region of the semiconductor device to bypass a next number of nonvolatile memory elements in the first selected region and applying test vectors to the elements controlled by the next number of bypassed nonvolatile memory elements; and continuing activating bypass circuitry in the first region of the semiconductor device to bypass subsequent numbers of nonvolatile memory elements in the first selected region and applying test vectors to the elements controlled by the subsequent numbers of bypassed nonvolatile memory elements until all elements controlled by nonvolatile memory elements in the first selected region have been tested.
Claim 2
Independent Claim
219 words
A method of testing regions of a semiconductor device having nonvolatile memory elements in control circuits wherein the control circuits control the state of elements in the semiconductor device, the method comprising: determining the probability of defects occurring in each region of the semiconductor device having nonvolatile memory elements in control circuits; placing the nonvolatile memory elements in a high impedance state; selecting a first region of the semiconductor device having the highest probability of containing a defect; activating bypass circuitry in the first region of the semiconductor device to bypass a number of nonvolatile memory elements in the first selected region and applying test vectors to the elements controlled by the number of bypassed nonvolatile memory elements; activating bypass circuitry in the first region of the semiconductor device to bypass a next number of nonvolatile memory elements in the first selected region and applying test vectors to the elements controlled by the next number of bypassed nonvolatile memory elements; and continuing activating bypass circuitry in the first region of the semiconductor device to bypass subsequent numbers of nonvolatile memory elements in the first selected region and applying test vectors to the elements controlled by the subsequent numbers of bypassed nonvolatile memory elements until all elements controlled by nonvolatile memory elements in the first selected region have been tested.
Claim 3
Dependent Claim
171 words
The method of claim 1, the method further comprising: selecting a next region of the semiconductor device having the next highest probability of containing a defect; activating bypass circuitry in the next region of the semiconductor device to bypass a number of nonvolatile memory elements in the next selected region and applying test vectors to the elements controlled by the number of bypassed nonvolatile memory elements in the next selected region; activating bypass circuitry in the next region of the semiconductor device to bypass a next number of nonvolatile memory elements in the next selected region and applying test vectors to the elements controlled by the number of bypassed nonvolatile memory elements in the next selected region; and continuing activating bypass circuitry in the next region of the semiconductor device to bypass subsequent numbers of nonvolatile memory elements in the next selected region and applying test vectors to the elements controlled by the subsequent numbers of bypassed nonvolatile memory elements until all elements in the next selected region have been tested.
Claim 4
Dependent Claim
27 words
The method of claim 2, the method further comprising continuing selecting next regions of the semiconductor device until all regions in the semiconductor device have been tested.
Claim 5
Dependent Claim
18 words
The method of claim 3, the method further comprising ceasing testing the semiconductor device when a test fails.
Claim 6
Dependent Claim
31 words
The method of claim 4, wherein bypassing a number of nonvolatile memory elements comprises supplying the same voltage levels to elements that would have been supplied by the nonvolatile memory elements.
Claim 7
Dependent Claim
29 words
The method of claim 5, wherein supplying the same voltage levels to elements is accomplished by modifying control circuits that control the state of elements in the semiconductor device.
Claim 8
Independent Claim
68 words
A method of testing a semiconductor device, the method comprising: selecting and testing a first region of the semiconductor device having a highest probability of containing a defect; selecting and testing a next region of the semiconductor device, having a next highest probability of containing a defect; and continuing selecting and testing next regions of the semiconductor device until all regions of the semiconductor device have been tested.
Claim 9
Independent Claim
68 words
A method of testing a semiconductor device, the method comprising: selecting and testing a first region of the semiconductor device having a highest probability of containing a defect; selecting and testing a next region of the semiconductor device, having a next highest probability of containing a defect; and continuing selecting and testing next regions of the semiconductor device until all regions of the semiconductor device have been tested.
Claim 10
Dependent Claim
51 words
A semiconductor device having enhanced testability, comprising: semiconductor elements; nonvolatile memory elements in control circuits that control the state of the semiconductor elements; and bypass circuitry that bypasses a number of the nonvolatile memory elements and applies test vectors to the elements controlled by the number of bypassed nonvolatile memory elements.
Claim 11
Dependent Claim
51 words
A semiconductor device having enhanced testability, comprising: semiconductor elements; nonvolatile memory elements in control circuits that control the state of the semiconductor elements; and bypass circuitry that bypasses a number of the nonvolatile memory elements and applies test vectors to the elements controlled by the number of bypassed nonvolatile memory elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |