Patent US5982669A successfully refreshed from Google Patents.
US5982669A
Expired / Lapsed
US
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EPROM and flash memory cells with source-side injection
Assignee: National Semiconductor Corp
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Filing: 1998-11-04
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Granted: 1999-11-09
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Expires: 2018-11-04
Abstract
Abstract An electrically-programmable read-only-memory (EPROM) and a flash memory cell provide both source-side and drain-side injection, along with a reduced cell size, by forming the memory cell in a trench. The drain is formed in the top surface of the substrate, the source is formed in the bottom surface of the trench, and the stacked gate is formed over the sidewall of the trench.
Inventors
- 👤 Alexander Kalnitsky
- 👤 Christoph Pichler
- 👤 Albert Bergemont
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:16
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; H; H10; H10B; H10B41/00; H10B41/20; H10B41/23; H10B69/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
267 words
A memory device comprising: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically and horizontally spaced-apart from the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically and horizontally spaced-apart from the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in four rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors.
Claim 2
Dependent Claim
267 words
A memory device comprising: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically and horizontally spaced-apart from the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically and horizontally spaced-apart from the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in four rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors.
Claim 3
Independent Claim
449 words
A method for programming a selected memory cell in a memory device, the memory device having: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically spaced-apart from and below the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically spaced-apart from and below the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells, the plurality of contacted bit lines including a contacted bit line connected to the drain of the selected memory cell and a plurality of remaining contacted bit lines; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in four rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells, the plurality of word lines including a selected word line connected to the control gate of the selected memory cell and a plurality of remaining word lines; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors, the plurality of access lines including a pair of selected access lines connected to access transistors connected to the source of the selected memory cell and unconnected to the drain of the selected memory cell, and a pair of remaining access lines, the method comprising the steps of: applying an access voltage to the pair of selected access lines; applying ground to the pair of remaining access lines; applying a drain voltage to the contacted bit line that is connected to the selected memory cell; applying ground to the remaining contacted bit lines; applying a programming voltage to the word line connected to the selected memory cell; and applying ground to the remaining word lines.
Claim 4
Independent Claim
449 words
A method for programming a selected memory cell in a memory device, the memory device having: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically spaced-apart from and below the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically spaced-apart from and below the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells, the plurality of contacted bit lines including a contacted bit line connected to the drain of the selected memory cell and a plurality of remaining contacted bit lines; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in four rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells, the plurality of word lines including a selected word line connected to the control gate of the selected memory cell and a plurality of remaining word lines; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors, the plurality of access lines including a pair of selected access lines connected to access transistors connected to the source of the selected memory cell and unconnected to the drain of the selected memory cell, and a pair of remaining access lines, the method comprising the steps of: applying an access voltage to the pair of selected access lines; applying ground to the pair of remaining access lines; applying a drain voltage to the contacted bit line that is connected to the selected memory cell; applying ground to the remaining contacted bit lines; applying a programming voltage to the word line connected to the selected memory cell; and applying ground to the remaining word lines.
Claim 5
Dependent Claim
21 words
The memory device of claim 1 wherein a word line is connected to each control gate in a row of cells.
Claim 6
Dependent Claim
269 words
A memory device comprising: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically and horizontally spaced-apart from the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically and horizontally spaced-apart from the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in a plurality of rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors.
Claim 7
Dependent Claim
269 words
A memory device comprising: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically and horizontally spaced-apart from the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically and horizontally spaced-apart from the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in a plurality of rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors.
Claim 8
Dependent Claim
21 words
The memory device of claim 4 wherein a word line is connected to each control gate in a row of cells.
Claim 9
Independent Claim
451 words
A method for programming a selected memory cell in a memory device, the memory device having: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically spaced-apart from and below the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically spaced-apart from and below the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells, the plurality of contacted bit lines including a contacted bit line connected to the drain of the selected memory cell and a plurality of remaining contacted bit lines; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in a plurality of rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells, the plurality of word lines including a selected word line connected to the control gate of the selected memory cell and a plurality of remaining word lines; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors, the method comprising the steps of: applying an access voltage to each access line connected to an access transistor that is connected to the source of the selected cell and unconnected to the drain of the selected cell; applying ground to each access line unconnected to an access transistor that is connected to the source of the selected cell and unconnected to the drain of the selected cell; applying a drain voltage to the contacted bit line that is connected to the selected memory cell; applying ground to the remaining contacted bit lines; applying a programming voltage to the word line connected to the selected memory cell; and applying ground to the remaining word lines.
Claim 10
Independent Claim
451 words
A method for programming a selected memory cell in a memory device, the memory device having: a plurality of memory cells arranged in rows and columns, each cell having a drain region, a source region vertically spaced-apart from and below the drain region, a channel region defined between the drain and source regions, a floating gate formed over the channel region, and a control gate formed over the floating gate, the floating gate and the control gate each having a first end and a second end which is vertically spaced-apart from and below the first end; a plurality of contacted bit lines connected to the drains of the cells such that each contacted bit line is connected to all of the drains in two adjacent columns of cells, the plurality of contacted bit lines including a contacted bit line connected to the drain of the selected memory cell and a plurality of remaining contacted bit lines; a plurality of non-contacted bit lines formed so that one non-contacted bit line is positioned between each pair of adjacent contacted bit lines, and connected to the sources of the cells such that each non-contacted bit line is connected to all of the sources in two adjacent columns of cells; a plurality of access transistors formed in a plurality of rows so that an access transistor is formed at each end of each column of memory cells, each row of access transistors being formed so that an access transistor is connected to every other pair of adjacent contacted and noncontacted bit lines; a plurality of word lines connected to the cells so that a word line is connected to each cell in a row of cells, the plurality of word lines including a selected word line connected to the control gate of the selected memory cell and a plurality of remaining word lines; a plurality of access lines connected to the access transistors so that an access line is connected to each access transistor in a row of access transistors, the method comprising the steps of: applying an access voltage to each access line connected to an access transistor that is connected to the source of the selected cell and unconnected to the drain of the selected cell; applying ground to each access line unconnected to an access transistor that is connected to the source of the selected cell and unconnected to the drain of the selected cell; applying a drain voltage to the contacted bit line that is connected to the selected memory cell; applying ground to the remaining contacted bit lines; applying a programming voltage to the word line connected to the selected memory cell; and applying ground to the remaining word lines.
Claim 11
Dependent Claim
20 words
The method of claim 4 wherein a word line is connected to each control gate in a row of cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |