Data compression and display memory apparatus

Claim 2

A data compression and display memory apparatus, comprising: a synchronous separator for separating a synchronous signal and a field signal from a luminance signal Y; a control signal generator for performing a control operation in accordance with an output from the synchronous separator; a DPCM (Differential Pulse Code Modulation) and quantization unit for quantizing 8-bit luminance signal Y and chrominance signal C, which is an ODD field signal, in accordance with a clock signal CK1 from the control signal generator for thus outputting 4-bit luminance signal Y and chrominance signal C; a bit converter for converting quantized 4-bit luminance signal Y and chrominance signal into 8-bit, respectively; a memory for storing an output from the bit converter in accordance with read/write signals RD and WR from the control signal generator; a bit converter for converting 8-bit luminance signal Y and chrominance signal C from the memory into 4-bit, respectively; a reverse DPCM and dequantization unit for reverse-DPCM-processing and dequantizing an output from the bit converter in accordance with the clock signal CK1 and outputting an ODD field signal; an interpolation unit for generating an EVEN field signal from the ODD field signal from the reverse DPCM and dequantization unit in accordance with the clock signal CK1; and a multiplexor for multiplexing the ODD field signal and EVEN field signal in accordance with a control signal CT from the control signal generator and outputting 8-bit luminance signal Y and chrominance signal C.

Claim 3

The apparatus of claim 1, wherein said reverse DPCM and dequantization unit includes: a subtractor for performing a subtraction with respect to the luminance signal Y of the coded ODD field and chrominance signal C and a prediction value p(n); a quantizer for quantizing an output from the subtractor; an adder for adding an output from the quantizer and the prediction value p(n); and a prediction unit for outputting a prediction value p(n) by multiplying an output from the adder and a weight.

Claim 4

The apparatus of claim 2, wherein said quantizer is formed of a ROM of 256×8-bit for thus receiving a subtracted value e(n) as an address and outputting a value matching with the address value.

Claim 5

The apparatus of claim 2, wherein said prediction unit includes: a line delay unit for line-delaying an output from the adder; a delay unit for sampling and delaying an output from the line delay unit; an adder for adding outputs from the line delay unit and the delay unit; a shift register for eliminating an LSB and the next LSB from an output from the adder; a delay unit for sampling and delaying an output from the adder; a shift register for eliminating an LSB from an output from the delay unit; and an adder for adding outputs from the shift registers.

Claim 6

The apparatus of claim 1, wherein said bit converter includes: a distributor for distributing a clock signal CK1 having a clock frequency of 4f sc from the control signal generator; first flip-flop units for latching an output from the quantizer in accordance with a clock signal CK2 from the distributor; and second flip-flop units for latching 4-bit data from the first flip-flop units in accordance with a clock signal CLK2 and outputting 8-bit data.

Claim 7

The apparatus of claim 1, wherein said reverse DPCM and dequantization unit includes: an adder for adding an output from the bit converter and a prediction value p(n); and a prediction unit for outputting a prediction value p(n) in accordance with a value which is obtained by multiplying an output from the adder by a weight.

Claim 8

The apparatus of claim 1, wherein said interpolation unit includes: a delay unit for sampling and delaying an output from the reverse DPCM and dequantization unit; an adder for adding an output from the delay unit and an output from the reverse DPCM and dequantization unit; and a shift register for eliminating an LSB and the next LSB from an output from the adder and generating an EVEN field signal.

Claim 9

A data compression and display memory apparatus, comprising: a synchronous separator for separating a synchronous signal and a field signal from a luminance signal Y; a control signal generator for performing a control operation in accordance with an output from the synchronous separator; a DPCM and quantization unit for quantizing 8-bit luminance signal Y and chrominance signal C, which is an ODD field signal, in accordance with a clock signal CK1 from the control signal generator for thus outputting 4-bit luminance signal Y and chrominance signal C; a bit converter for converting quantized 4-bit luminance signal Y and chrominance signal into 8-bit, respectively; a memory for storing an output from the bit converter in accordance with read/write signals RD and WR from the control signal generator; a bit converter for converting 8-bit luminance signal Y and chrominance signal C from the memory into 4-bit, respectively; a reverse DPCM and dequantization unit for reverse-DPCM-processing and dequantizing an output from the bit converter in accordance with the clock signal CK1 and outputting an ODD field signal; an interpolation unit for generating an EVEN field signal from the ODD field signal from the reverse DPCM and dequantization unit in accordance with the clock signal CK1; a multiplexor for multiplexing the ODD field signal and EVEN field signal in accordance with a control signal CT from the control signal generator and outputting 8-bit luminance signal Y and chrominance signal C; and a reverse DPCM unit for reverse-DPCM-processing a differential signal from the multiplexor and outputting 8-bit luminance signal Y and chrominance signal C.

Claim 10

A data compression and display memory apparatus, comprising: a synchronous separator for separating a synchronous signal and a field signal from a luminance signal Y; a control signal generator for performing a control operation in accordance with an output from the synchronous separator; a DPCM and quantization unit for quantizing 8-bit luminance signal Y and chrominance signal C, which is an ODD field signal, in accordance with a clock signal CK1 from the control signal generator for thus outputting 4-bit luminance signal Y and chrominance signal C; a bit converter for converting quantized 4-bit luminance signal Y and chrominance signal into 8-bit, respectively; a memory for storing an output from the bit converter in accordance with read/write signals RD and WR from the control signal generator; a bit converter for converting 8-bit luminance signal Y and chrominance signal C from the memory into 4-bit, respectively; a reverse DPCM and dequantization unit for reverse-DPCM-processing and dequantizing an output from the bit converter in accordance with the clock signal CK1 and outputting an ODD field signal; an interpolation unit for generating an EVEN field signal from the ODD field signal from the reverse DPCM and dequantization unit in accordance with the clock signal CK1; a multiplexor for multiplexing the ODD field signal and EVEN field signal in accordance with a control signal CT from the control signal generator and outputting 8-bit luminance signal Y and chrominance signal C; and a reverse DPCM unit for reverse-DPCM-processing a differential signal from the multiplexor and outputting 8-bit luminance signal Y and chrominance signal C.

Claim 11

A data compression and display memory apparatus, comprising: horizontal and vertical decimation units for decimating sampled 8-bit luminance signal Y and chrominance signal C twice in the horizontal direction and triple in the vertical direction for being adapted to a PIP mode; a horizontal decimation unit for twice decimating outputs from the horizontal and vertical decimation units in the horizontal direction; a synchronous separator for separating a synchronous signal and a field signal from a luminance signal Y; a control signal generator for performing a control operation in accordance with an output from the synchronous separator; a DPCM and quantization unit for quantizing 8-bit luminance signal Y and chrominance signal C, which is an ODD field signal, in accordance with a clock signal CK1 from the control signal generator for thus outputting 4-bit luminance signal Y and chrominance signal C; a bit converter for converting quantized 4-bit luminance signal Y and chrominance signal into 8-bit, respectively; a memory for storing an output from the bit converter in accordance with read/write signals RD and WR from the control signal generator; a bit converter for converting 8-bit luminance signal Y and chrominance signal C from the memory into 4-bit, respectively; a reverse DPCM and dequantization unit for reverse-DPCM-processing and dequantizing an output from the bit converter in accordance with the clock signal CK1 and outputting an ODD field signal; an interpolation unit for generating an EVEN field signal from the ODD field signal from the reverse DPCM and dequantization unit in accordance with the clock signal CK1; and a multiplexor for multiplexing the ODD field signal and EVEN field signal in accordance with a control signal CT from the control signal generator and outputting 8-bit luminance signal Y and chrominance signal C.

Claim 12

A data compression and display memory apparatus, comprising: horizontal and vertical decimation units for decimating sampled 8-bit luminance signal Y and chrominance signal C twice in the horizontal direction and triple in the vertical direction for being adapted to a PIP mode; a horizontal decimation unit for twice decimating outputs from the horizontal and vertical decimation units in the horizontal direction; a synchronous separator for separating a synchronous signal and a field signal from a luminance signal Y; a control signal generator for performing a control operation in accordance with an output from the synchronous separator; a DPCM and quantization unit for quantizing 8-bit luminance signal Y and chrominance signal C, which is an ODD field signal, in accordance with a clock signal CK1 from the control signal generator for thus outputting 4-bit luminance signal Y and chrominance signal C; a bit converter for converting quantized 4-bit luminance signal Y and chrominance signal into 8-bit, respectively; a memory for storing an output from the bit converter in accordance with read/write signals RD and WR from the control signal generator; a bit converter for converting 8-bit luminance signal Y and chrominance signal C from the memory into 4-bit, respectively; a reverse DPCM and dequantization unit for reverse-DPCM-processing and dequantizing an output from the bit converter in accordance with the clock signal CK1 and outputting an ODD field signal; an interpolation unit for generating an EVEN field signal from the ODD field signal from the reverse DPCM and dequantization unit in accordance with the clock signal CK1; and a multiplexor for multiplexing the ODD field signal and EVEN field signal in accordance with a control signal CT from the control signal generator and outputting 8-bit luminance signal Y and chrominance signal C.

Claim 13

The apparatus of claim 9, wherein said horizontal decimation unit includes: two delay units for delaying sampled 8-bit luminance signal Y and chrominance signal C by one pixel, respectively; an adder for adding outputs from the delay units; and a shift register for eliminating an LSB from an output from the adder.

Claim 14

The apparatus of claim 9, wherein said vertical decimation unit includes: two delay units for delaying an output from the horizontal decimation unit by 336 pixels; a first adder for adding outputs from the delay units and an output from the horizontal decimation unit; shift registers for eliminating an LSB from an output from the first adder; a first delay unit for delaying an output from the shift register by 3-pixel; a second delay unit for delaying an output from the shift register by one-pixel; and a second adder for adding an output from the shift register and outputs from the delay units.

Claim 15

A data compression and display memory apparatus, comprising: a horizontal and vertical decimation unit for twice decimating a sampled 8-bit luminance signal Y and chrominance signal C in the horizontal direction and triple decimating the same in the vertical direction; a horizontal decimation unit for twice decimating an output from the vertical decimation unit in the horizontal direction; a DPCM and coding unit for performing a DPCM with respect to an output from the horizontal decimation unit and coding the data into a 4-bit data; a bit converter for converting an output from the DPCM and coding unit into an 8-bit data; a memory for storing an output from the bit converter; a bit converter for converting an 8-bit data from the memory into a 4-bit data; a reverse DPCM and coding unit for performing a reverse DPCM with respect to an output from the bit converter and coding the same; a horizontal and vertical interpolation unit for receiving an output from the reverse DPCM and coding unit, performing a horizontal and vertical axis interpolation with respect to the horizontal and vertical decimation, and outputting a luminance signal Y and chrominance signal C of an ODD field; an EVEN field generation unit for vertically interpolating an output from the horizontal and vertical interpolation unit and generating an EVEN field; and a multiplexor for multiplexing an ODD field from the horizontal and vertical interpolation unit and an EVEN field from the EVEN field generation unit and outputting an 8-bit luminance signal Y and chrominance signal C.

Claim 16

A data compression and display memory apparatus, comprising: a horizontal and vertical decimation unit for twice decimating a sampled 8-bit luminance signal Y and chrominance signal C in the horizontal direction and triple decimating the same in the vertical direction; a horizontal decimation unit for twice decimating an output from the vertical decimation unit in the horizontal direction; a DPCM and coding unit for performing a DPCM with respect to an output from the horizontal decimation unit and coding the data into a 4-bit data; a bit converter for converting an output from the DPCM and coding unit into an 8-bit data; a memory for storing an output from the bit converter; a bit converter for converting an 8-bit data from the memory into a 4-bit data; a reverse DPCM and coding unit for performing a reverse DPCM with respect to an output from the bit converter and coding the same; a horizontal and vertical interpolation unit for receiving an output from the reverse DPCM and coding unit, performing a horizontal and vertical axis interpolation with respect to the horizontal and vertical decimation, and outputting a luminance signal Y and chrominance signal C of an ODD field; an EVEN field generation unit for vertically interpolating an output from the horizontal and vertical interpolation unit and generating an EVEN field; and a multiplexor for multiplexing an ODD field from the horizontal and vertical interpolation unit and an EVEN field from the EVEN field generation unit and outputting an 8-bit luminance signal Y and chrominance signal C.