Linearizing offset cancelling white balancing and gamma correcting analog to digital converter for active pixel sensor imagers with self calibrating and self adjusting properties

Claim 2

A signal processing circuit highly immune to manufacturing variations and variations in operating conditions for outputting a digital word corresponding to a physical stimulus controlled current source, said circuit comprising: an analog integrator circuit responsive to said physical stimulus controlled current source for outputting a first signal representative of said physical stimulus controlled current source; a reference signal generator circuit responsive to a constant current source for outputting a second signal, said second signal being a ramp signal; an output circuit including a comparator for receiving said first and said second signals and for comparing said first signal against said second signal, said output circuit also including a counter for generating said digital word representative of a time interval defined by a start signal and an end signal, said end signal representing a transition of the output of the comparator; and the reference signal generator circuit and the analog integrator circuit being parts of a semiconductor integrated circuit fabricated on a single semiconductor substrate, and the reference signal generator being a scaled replica of the analog integrator circuit.

Claim 3

The invention of claim 1 wherein said physical stimulus controlled current source is a first photo-sensor device.

Claim 4

The invention of claim 2, further including an operating cycle for said reference signal generator circuit, said operating cycle including a ramp output phase and the initial value of the output of the reference signal generator circuit is an operating variable.

Claim 5

The invention of claim 3 wherein the output of the analog integrator circuit is offset by a component attributable to dark-current generated by said photo-sensor device.

Claim 6

The invention of claim 4 further comprising a second photo-sensor device, said second photo-sensor device being a blinded photo-sensor device, said first photo-sensor device and said second photo-sensor device being semiconductor devices fabricated on a common semiconductor substrate, and the second photo-sensor device being a scaled replica of said first photo-sensor device; and the initial value of the output of the reference signal generator circuit being generated by causing said generator circuit to integrate the output of the second photo-sensor over a predetermined time interval.

Claim 7

The invention of claim 5 wherein the output of the signal processing circuit has a predetermined functional relationship (circuit response function) to the output of the first photo-sensor device, the circuit response function being determined by a clock signal input to the counter of said output circuit, and the phase of said clock signal being a predetermined function of time.

Claim 8

The invention of claim 1 wherein said signal processing circuit is a semiconductor integrated circuit fabricated on a single semiconductor substrate.

Claim 9

The invention of claim 7 wherein said semiconductor integrated circuit comprises an array of signal processing circuits.

Claim 10

The invention of claim 8 wherein both said reference signal generator circuit and said output circuit in at least one of the array of signal processing circuits is time shared by a number of analog integrator circuits.

Claim 11

The invention of claim 9 wherein the value of the constant current source is an operating parameter updatable prior to execution of a ramp output phase of an operating cycle.

Claim 12

The invention of claim 10 wherein the array of signal processing circuits is organized in sets, each set being dedicated to sensing one segment of input radiation spectrum, and the value of the constant current source being selected so as to cause the output circuit to produce a predetermined output when the array is stimulated with white (flat spectrum) radiation of a predetermined intensity.

Claim 13

A semiconductor integrated Analog to Digital (A/D) converter circuit comprising: an analog comparator; a digital counter; a reference ramp generator; a constant current source; and a signal generator; wherein the analog comparator compares the output of the reference ramp generator to an analog input signal; the digital counter counts cycles of an input clock signal; the reference ramp generator is driven by the constant current source; the reference ramp generator responds to the driving constant current source by generating a predetermined monotonic function of time (ramp function); the initial value of the ramp function is an operating variable; the value of the constant current source is an operating parameter; the A/D converter operating cycle has at least two phases, a reset phase and an active phase; the ramp generator and the digital counter are simultaneously initialized during the reset phase; the ramp generator comprises a scaled replica of the signal generator circuit; the signal generator generates an output in response to a physical stimulus continuously applied to the converter circuit; and an output of the A/D converter is a count attained by the digital counter during a time interval beginning with the onset of the active phase of an A/D converter operating cycle, and ending on an analog comparator output transition.

Claim 14

A semiconductor integrated Analog to Digital (A/D) converter circuit comprising: an analog comparator; a digital counter; a reference ramp generator; a constant current source; and a signal generator; wherein the analog comparator compares the output of the reference ramp generator to an analog input signal; the digital counter counts cycles of an input clock signal; the reference ramp generator is driven by the constant current source; the reference ramp generator responds to the driving constant current source by generating a predetermined monotonic function of time (ramp function); the initial value of the ramp function is an operating variable; the value of the constant current source is an operating parameter; the A/D converter operating cycle has at least two phases, a reset phase and an active phase; the ramp generator and the digital counter are simultaneously initialized during the reset phase; the ramp generator comprises a scaled replica of the signal generator circuit; the signal generator generates an output in response to a physical stimulus continuously applied to the converter circuit; and an output of the A/D converter is a count attained by the digital counter during a time interval beginning with the onset of the active phase of an A/D converter operating cycle, and ending on an analog comparator output transition.

Claim 15

A semiconductor integrated circuit according to the invention of claim 12 wherein: said applied physical stimulus comprises a physical stimulus controlled current source (sensor device); the signal generator generates output in response to the physical stimulus applied to the sensor device; and the signal generator generates a monotonic function of time while physical stimulus is applied to the sensor device.

Claim 16

The invention of claim 13, wherein the signal generator circuit is an active integrator.

Claim 17

The invention of claim 14, wherein the sensor device is a photo-sensor, and the combination of sensor device and active integrator circuit functions as an active photo-integrator.

Claim 18

The invention of claim 15, wherein: the output of the active integrator is offset by a component attributable to dark-current produced by the photo-sensor; and the value of this offset is used as the initial value of the ramp function.

Claim 19

The invention of claim 16, further comprising a blinded photo-sensor, and wherein: the initial value of the ramp function is generated by causing the reference ramp generator to integrate the output of the blinded photo-sensor over a predetermined time interval.

Claim 20

The invention of claim 12, wherein the phase of the clock generator circuit is a predetermined function of time.

Claim 21

The invention of claim 18 wherein: f c is a constant scaling factor; γ is a predetermined constant; and the phase φ(t) of the clock generator circuit is defined by the following function f time t: φ(t)=2π(f.sub.c *t).sup.γ 20.

Claim 22

A semiconductor integrated circuit comprising an array of A/D converters according to claim 12 and an array of signal generating sources, wherein a signal generating source comprises: said signal generator; a physical stimulus controlled current source (sensor device); and wherein, the signal generator generates output in response to physical stimulus applied to the sensor device; the signal generator generates a monotonic function of time while physical stimulus is applied to the sensor device; and each ramp generator in each instance of an A/D converter is a scaled replica of the signal generator.

Claim 23

The invention of claim 20 wherein the array of A/D converters is of a lesser size than the array of signal generating sources; and each A/D converter is time shared by a set of signal generating sources.

Claim 24

The invention of claim 21 wherein: the value of the constant current source is independently set for each A/D converter of the array, and the value of each constant current source is updatable prior to executing an operating cycle of the A/D converter.

Claim 25

The invention of claim 22, wherein the array of signal generating sources is organized in sets; each set is dedicated to sensing one segment of input radiation spectrum; and the value of the constant current source of all the A/D converters time-shared by signal generators in the same set is the same.

Claim 26

The invention of claim 23, wherein the value of the constant source of each A/D converter is selected such as to cause each A/D converter to produce the same output count when the array is stimulated with constant, white (flat spectrum) radiation.

Claim 27

A semiconductor integrated circuit comprising an Analog to Digital (A/D) converter circuit of the single slope integration type, wherein said A/D converter comprises: an analog comparator subcircuit having an analog signal input terminal, an analog reference input terminal, and a digital signal output terminal; a digital counter subcircuit, having a clock signal input terminal, a control enable input terminal, and a control reset input terminal, wherein a phase of a clock generator circuit generating said clock signal is a predetermined function of time; a ramp generator subcircuit having a signal input terminal, a signal output terminal, and a control reset input terminal; a reference constant current generator; and wherein the digital output of the analog comparator circuit is connected to the enable terminal of the digital counter subcircuit; the output of the ramp generator subcircuit is connected to the reference input terminal of the analog comparator subcircuit; the input terminal of the ramp generator is connected to the reference constant current generator; the subcircuits and the current source share a common signal reference node (circuit ground node); the input terminal of the A/D converter is the input terminal of the analog comparator subcircuit; the response of the ramp generator circuit to the input constant current generated by the reference constant current generator is a predetermined monotonic function of time (ramp signal); an A/D converter operating cycle has at least two phases, a reset phase and a ramping phase; the digital counter subcircuit and the ramp generator subcircuit are simultaneously reset during the reset phase of the operating cycle; at the onset of the ramping phase of an operating cycle, the ramp generator is enabled to generate output simultaneously as the digital counter is enabled to count clock signal pulses; the ramp generator output assumes a predetermined value at the beginning of the ramping phase; the value assumed by the output of the ramp generator at the beginning of the ramping phase is an operating variable of the A/D converter circuit; the value of the constant current source connected to the input of the ramp generator is an operating variable of the A/D converter circuit; an output of the A/D converter circuit is a count of the digital counter subcircuit; and an output of the A/D converter circuit is a count attained by the digital counter in a time interval beginning with an onset of a ramping phase of an operating cycle and ending within the same ramping phase on the occasion of a transition of the digital output of the analog comparator subcircuit.

Claim 28

A semiconductor integrated circuit comprising an Analog to Digital (A/D) converter circuit of the single slope integration type, wherein said A/D converter comprises: an analog comparator subcircuit having an analog signal input terminal, an analog reference input terminal, and a digital signal output terminal; a digital counter subcircuit, having a clock signal input terminal, a control enable input terminal, and a control reset input terminal, wherein a phase of a clock generator circuit generating said clock signal is a predetermined function of time; a ramp generator subcircuit having a signal input terminal, a signal output terminal, and a control reset input terminal; a reference constant current generator; and wherein the digital output of the analog comparator circuit is connected to the enable terminal of the digital counter subcircuit; the output of the ramp generator subcircuit is connected to the reference input terminal of the analog comparator subcircuit; the input terminal of the ramp generator is connected to the reference constant current generator; the subcircuits and the current source share a common signal reference node (circuit ground node); the input terminal of the A/D converter is the input terminal of the analog comparator subcircuit; the response of the ramp generator circuit to the input constant current generated by the reference constant current generator is a predetermined monotonic function of time (ramp signal); an A/D converter operating cycle has at least two phases, a reset phase and a ramping phase; the digital counter subcircuit and the ramp generator subcircuit are simultaneously reset during the reset phase of the operating cycle; at the onset of the ramping phase of an operating cycle, the ramp generator is enabled to generate output simultaneously as the digital counter is enabled to count clock signal pulses; the ramp generator output assumes a predetermined value at the beginning of the ramping phase; the value assumed by the output of the ramp generator at the beginning of the ramping phase is an operating variable of the A/D converter circuit; the value of the constant current source connected to the input of the ramp generator is an operating variable of the A/D converter circuit; an output of the A/D converter circuit is a count of the digital counter subcircuit; and an output of the A/D converter circuit is a count attained by the digital counter in a time interval beginning with an onset of a ramping phase of an operating cycle and ending within the same ramping phase on the occasion of a transition of the digital output of the analog comparator subcircuit.

Claim 29

A semiconductor integrated circuit according to the invention of claim 25, further comprising: a signal generator subcircuit having a signal input terminal, a signal output terminal, and a control (timing) reset input terminal; a signal current source controlled by a physical stimulus; and wherein, the signal current source is connected to the input terminal of the signal subcircuit; the signal generator subcircuit and the current source share a common reference node; the reference node shared by the signal generator subcircuit and the signal current source is the common signal reference node (circuit ground node); the output terminal of the signal generator subcircuit is connected to the input terminal of the A/D converter subcircuit; an operating cycle of the signal generator subcircuit has at least two phases, a reset phase, and an active phase; during the reset phase of the operating cycle of the signal generator subcircuit, the output of the signal generator subcircuit is set to a predetermined value; during the active phase of the operating cycle of the signal subcircuit the signal generator subcircuit responds monotonically to the signal current source; an A/D converter cycle is executed at the end of an operating cycle of the signal generator subcircuit; the output of an A/D converter cycle is a digital word representing a weighted average value of current generated by the signal current source during the active phase of the operating cycle of the signal subcircuit; an operating cycle of the signal generating subcircuit is executed by timing circuits under the control of a digital controller; an operating cycle of the A/D converter is aligned with respect to an operating cycle of the signal subcircuit by timing circuits operating under the control of a digital controller.

Claim 30

A semiconductor integrated circuit according to the invention of claim 26, wherein the signal generator subcircuit and the ramp generator subcircuit are identical circuits.

Claim 31

A semiconductor integrated circuit according to the invention of claim 27, wherein the signal generator subcircuit is an active integrator.

Claim 32

A semiconductor integrated circuit according to the invention of claim 28, wherein the signal current source is a photo-sensor.

Claim 33

A semiconductor integrated circuit according to the invention of claim 29, wherein the combination of a photo-integrator circuit and signal current source is an active photo-integrator subcircuit.

Claim 34

A semiconductor integrated circuit comprising an array of photo-integrator subcircuits and an array of A/D converter subcircuits according to the invention of claim 30.

Claim 35

A semiconductor integrated circuit according to the invention of claim 31, comprising a two dimensional array of photo-integrator subcircuits and an one dimensional array of A/D converter subcircuits, and wherein: each A/D converter subcircuit is dedicated to converting the output of a subset of photo-integrator subcircuits; each A/D converter is time-shared by the photo-integrator subcircuits in the set to which it is dedicated.

Claim 36

A semiconductor integrated circuit according to the invention of claim 32, wherein the value of the reference constant current generator takes a value that is individually predetermined for each A/D converter subcircuit.

Claim 37

A semiconductor integrated circuit according to the invention of claim 33, wherein the array of photo-integrator circuits is organized in overlapping sets of photo-integrators and wherein: each set is dedicated to sensing one segment of input radiation spectrum.

Claim 38

A semiconductor integrated circuit according to the invention of claim 34, wherein the reference constant current generator circuits of the A/D converter array take predetermined values such as to cause the A/D conversion process to produce equalized (white balanced) response across the input radiation spectrum.

Claim 39

A semiconductor integrated circuit according to the invention of claim 29, further comprising: a blinded photosensor; and wherein: the blinded photo-sensor is connected in parallel with the reference constant current generator; the operating cycle of the ramp generator subcircuit has at least three phases, a reset phase, an offset generation phase, and a ramp generation phase; during the offset generation phase, the reference constant current generator is rendered inactive; current flowing through the blinded photo-sensor during the offset generating phase of the operating cycle of the ramp generator subcircuit generates a ramp generator output; the final value of the ramp generator output generated during the offset generation phase of the operating cycle of the ramp generating subcircuit is the initial value of the ramp generator output generated by the ramp generator subcircuit during the ramp generation phase of the ramp generating subcircuit.

Claim 40

A semiconductor integrated circuit according to the invention of claim 25 wherein: f c is a constant scaling factor; γ is a predetermined constant; and the phase φ(t) of the clock generator circuit is defined by the following function of time t: φ(t)=2π(f.sub.c *t).sup.γ

Claim 41

A semiconductor integrated circuit according to the invention of claim 25, further comprising: a signal generator subcircuit having a signal input terminal, a signal output terminal, and a control (timing) reset input terminal; a sample and hold (S/H) subcircuit, having a signal input terminal, a signal output terminal, and a control (timing) sample/hold terminal; a signal current source controlled by a physical stimulus; and wherein the signal current source is connected to the input terminal of the signal subcircuit; the signal generator subcircuit, the sample and hold subcircuit, and the signal current source share a common reference node; the signal output terminal of the signal generator subcircuit is connected to the signal input terminal of the S/H subcircuit; the signal output of the S/H converter subcircuit is connected to the signal input generator of the A/D subcircuit; the reference node shared by the signal generator subcircuit, the S/H subcircuit, and the signal current source is the common signal reference node (circuit ground node); an operating cycle of the sample and hold subcircuit has at least two phases, a sampling phase and a hold phase; an operating cycle of the signal generator subcircuit has at least two phases, a reset phase, and an active phase; during the reset phase of the operating cycle of the signal generator subcircuit, the output of the signal generator subcircuit is set to a predetermined value; during the active phase of the operating cycle of the signal subcircuit the signal generator subcircuit responds monotonically to the signal current source; an operating cycle of the sample and hold subcircuit is executed during the active phase of the operating cycle of the signal generator circuit; an A/D converter operating cycle is executed upon completion of a said operating cycle of the sample and hold subcircuit; the output of an A/D converter cycle is a digital word representing a weighted average value of current generated by the signal current source during the portion of the active phase of the operating cycle of the signal subcircuit, beginning with at the beginning of the active phase of the operating cycle of the signal generating subcircuit and ending at the beginning of the hold phase of the operating cycle of the sample and hold subcircuit; an operating cycle of the signal subcircuit is executed by timing circuits under the control of a system controller; an operating cycle of the sample and hold subcircuit is aligned with respect to an operating cycle of the signal generating subcircuit by timing circuits under the control of a system controller; an operating cycle of the A/D converter is aligned with respect to an operating cycle of the sample and hold subcircuit by timing circuits operating under the control of a system controller.

Claim 42

A signal processing circuit highly immune to manufacturing variations and variations in operating conditions for outputting a digital word corresponding to stimulus applied to a photo-sensor device, said circuit comprising: an analog integrator circuit responsive to said photo-sensor device for outputting a first signal representative of said device; a reference signal generator circuit responsive to a constant current source for generating a second signal, said second signal being a ramp signal and the reference signal generator being a scaled replica of the analog integrator circuit; and an output circuit including a comparator for receiving said first and said second signals and for comparing the level of said first signal against the level of said second signal, said output circuit also including a counter for generating said digital word representative of a time interval defined by a start signal and an end signal, said end signal representing a transition of the output of the comparator.

Claim 43

A signal processing circuit highly immune to manufacturing variations and variations in operating conditions for outputting a digital word corresponding to stimulus applied to a photo-sensor device, said circuit comprising: an analog integrator circuit responsive to said photo-sensor device for outputting a first signal representative of said device; a reference signal generator circuit responsive to a constant current source for generating a second signal, said second signal being a ramp signal and the reference signal generator being a scaled replica of the analog integrator circuit; and an output circuit including a comparator for receiving said first and said second signals and for comparing the level of said first signal against the level of said second signal, said output circuit also including a counter for generating said digital word representative of a time interval defined by a start signal and an end signal, said end signal representing a transition of the output of the comparator.