Optimized frequency shaping circuit topologies for LDOs

Claim 1

A regulator, comprising: an error amplifier having a first input for receiving a reference voltage, a second input, and an output; a pass element having a control terminal coupled to said output of said error amplifier and a current path coupled between an input voltage and an output terminal; a pair of resistors coupled in series between said output terminal and ground, said second input of said error amplifier coupled to a first node between said pair of resistors; a load coupled to said output terminal between said pass element and said pair of resistors; said regulator having an open loop frequency response including a first pole at a first frequency, a second pole at a second frequency greater than said first frequency, a first zero at a third frequency greater than said second frequency a third pole at a fourth frequency greater than said third frequency, a second zero at a fifth frequency greater than said fourth freguency, and a fourth pole at a sixth frequency greater than said fifth frequency; said error amplifier providing the second zero in the open loop frequency response of the regulator.