Patent US5982192A successfully refreshed from Google Patents.
US5982192A
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High speed bus circuit system
Assignee: Mitsubishi Electric Corp
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Filing: 1998-01-30
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Granted: 1999-11-09
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Expires: 2018-01-30
Abstract
Abstract A high speed bus circuit system according to the present invention includes a bus having alternately connected resistors and transmission lines, and integrated circuits. Each of the resistors has a predetermined resistance value. The transmission lines are mounted on print circuit boards. The bus is connected in a loop form as a whole. Each of the integrated circuits has a driver and a receiver. The driver and receiver are connected to respective one of the resistors. As a result, DC power dissipation in the terminal resistor of the bus circuit is suppressed. In addition, high speed signal transfer causing less waveform distortion is made possible.
Inventors
- 👤 Seiichi Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:37
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4086; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
68 words
A high speed bus circuit system comprising: a bus including alternately connected resistors and transmission lines, each of said resistors having a predetermined resistance value, said transmission lines being mounted on print circuit boards, said bus being connected in a loop form as a whole; and integrated circuits each having a driver and a receiver, said driver and said receiver being connected to respective one of said resistors.
Claim 2
Dependent Claim
68 words
A high speed bus circuit system comprising: a bus including alternately connected resistors and transmission lines, each of said resistors having a predetermined resistance value, said transmission lines being mounted on print circuit boards, said bus being connected in a loop form as a whole; and integrated circuits each having a driver and a receiver, said driver and said receiver being connected to respective one of said resistors.
Claim 3
Dependent Claim
53 words
The high speed bus circuit system according to claim 1, wherein respective one of said integrated circuits is connected to only one end of each of said resistors so that corresponding one of said resistors may act as a terminal resistor and a sending-end resistor when one of said drivers drives said bus.
Claim 4
Dependent Claim
28 words
The high speed bus circuit system according to claim 2, wherein respective one of said integrated circuits is connected to only one end of each of said resistors.
Claim 5
Dependent Claim
31 words
The high speed bus circuit system according to claim 2, wherein a plurality of ones out of said integrated circuits are connected to only one end of each of said resistors.
Claim 6
Dependent Claim
52 words
The high speed bus circuit system according to claim 1, wherein respective ones of said integrated circuits are connected to each end of each of said resistors so that corresponding one of said resistors may act as a terminal resistor and a sending-end resistor when one of said drivers drives said bus.
Claim 7
Dependent Claim
27 words
The high speed bus circuit system according to claim 5, wherein respective one of said integrated circuits is connected to each end of each of said resistors.
Claim 8
Dependent Claim
30 words
The high speed bus circuit system according to claim 5, wherein a plurality of ones out of said integrated circuits are connected to each end of each of said resistors.
Claim 9
Dependent Claim
108 words
A high speed bus circuit system comprising: a first bus and a second bus each including alternately connected resistors and transmission lines, each of said resistors having a predetermined resistance value, said transmission lines being mounted on print circuit boards, each of said first bus and said second bus being connected in a loop form as a whole; and integrated circuits each having a differential driver and a differential receiver, a plus side of said driver and said receiver being connected to respective one resistor of said first bus, a minus side of said driver and said receiver being connected to respective one resistor of said second bus.
Claim 10
Dependent Claim
108 words
A high speed bus circuit system comprising: a first bus and a second bus each including alternately connected resistors and transmission lines, each of said resistors having a predetermined resistance value, said transmission lines being mounted on print circuit boards, each of said first bus and said second bus being connected in a loop form as a whole; and integrated circuits each having a differential driver and a differential receiver, a plus side of said driver and said receiver being connected to respective one resistor of said first bus, a minus side of said driver and said receiver being connected to respective one resistor of said second bus.
Claim 11
Dependent Claim
80 words
A high speed bus circuit system comprising: a bus including alternately connected resistors and transmission lines, each of said resistors having a predetermined resistance value, said transmission lines being mounted on print circuit boards, said bus being connected in a loop form as a whole; and integrated circuits each having a driver and a receiver disconnected from each other, said driver and said receiver being respectively connected to one end and the other end of respective one of said resistors.
Claim 12
Dependent Claim
80 words
A high speed bus circuit system comprising: a bus including alternately connected resistors and transmission lines, each of said resistors having a predetermined resistance value, said transmission lines being mounted on print circuit boards, said bus being connected in a loop form as a whole; and integrated circuits each having a driver and a receiver disconnected from each other, said driver and said receiver being respectively connected to one end and the other end of respective one of said resistors.
Claim 13
Dependent Claim
52 words
The high speed bus circuit system according to claim 9, further comprising an abnormality detector for outputting data to a driver of a specific integrated circuit, receiving data from a receiver of said specific integrated circuit, comparing the outputted data with the received data, and thereby detecting an abnormality of said bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |