Method for fabricating a high bias device compatible with a low bias device

Claim 1

A method for fabricating a high-bias device which is compatibly fabricated with a low-bias device, the method comprising: providing a substrate doped with a first-type dopant, wherein the substrate comprises a high-bias region and a low-bias region; forming an oxide layer over the substrate; forming a first well doped with a second-type dopant in the substrate, wherein the first well further comprises a high-bias well at the high-bias region and a low-bias well at the low-bias region, and the second-type dopant is different from the first-type dopant; simultaneously forming at least two second wells in the high-bias well and a third well in the low-bias well, wherein a first-type dopant is doped in the second wells and the third well; removing the oxide layer and forming a pad oxide layer over the substrate; forming a silicon nitride layer on the pad oxide layer; patterning the silicon nitride layer to form a plurality of exposed portions of the pad oxide layer at the high-bias region and the low-bias region; forming a plurality of field oxide (FOX) layers on the exposed portions of the pad oxide layer; removing the silicon nitride layer; removing the pad oxide layer; simultaneously forming a first gate oxide layer on the high-bias well between the second wells, and a second gate oxide layer on the third well between two of the FOX layers within the third well; simultaneously forming a first gate on the first gate oxide layer, and a second gate on the second gate oxide layer, wherein the first gate fully covers the first gate oxide layer and the second gate covers the second gate oxide layer at about the middle region; and simultaneously forming a first source region and a first drain region separately in the second wells, a second source region and a second drain region below the second gate oxide layer in the third well at each side of the second gate, and a plurality of variously doped regions in the substrate; wherein if the first-type dopant is an N-type dopant then the second-type dopant is a P-type dopant, and if the first-type dopant is a P-type dopant then the second-type dopant is an N-type dopant.

Claim 2

A method for fabricating a high-bias device which is compatibly fabricated with a low-bias device, the method comprising: providing a substrate doped with a first-type dopant, wherein the substrate comprises a high-bias region and a low-bias region; forming an oxide layer over the substrate; forming a first well doped with a second-type dopant in the substrate, wherein the first well further comprises a high-bias well at the high-bias region and a low-bias well at the low-bias region, and the second-type dopant is different from the first-type dopant; simultaneously forming at least two second wells in the high-bias well and a third well in the low-bias well, wherein a first-type dopant is doped in the second wells and the third well; removing the oxide layer and forming a pad oxide layer over the substrate; forming a silicon nitride layer on the pad oxide layer; patterning the silicon nitride layer to form a plurality of exposed portions of the pad oxide layer at the high-bias region and the low-bias region; forming a plurality of field oxide (FOX) layers on the exposed portions of the pad oxide layer; removing the silicon nitride layer; removing the pad oxide layer; simultaneously forming a first gate oxide layer on the high-bias well between the second wells, and a second gate oxide layer on the third well between two of the FOX layers within the third well; simultaneously forming a first gate on the first gate oxide layer, and a second gate on the second gate oxide layer, wherein the first gate fully covers the first gate oxide layer and the second gate covers the second gate oxide layer at about the middle region; and simultaneously forming a first source region and a first drain region separately in the second wells, a second source region and a second drain region below the second gate oxide layer in the third well at each side of the second gate, and a plurality of variously doped regions in the substrate; wherein if the first-type dopant is an N-type dopant then the second-type dopant is a P-type dopant, and if the first-type dopant is a P-type dopant then the second-type dopant is an N-type dopant.