← Back to Patent Explorer
US5976912A Expired / Lapsed US ⏱️ 0.0 years remaining

Fabrication process of semiconductor package and semiconductor package

Assignee: Resonac Corp
•
Filing: 1995-03-17
•
Granted: 1999-11-02
•
Expires: 2015-03-17
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Inventors

  • 👤 Naoki Fukutomi
  • 👤 Yoshiaki Tsubomatsu
  • 👤 Fumio Inoue
  • 👤 Toshio Yamazaki
  • 👤 Hirohito Ohhata
  • 👤 Shinsuke Hagiwara
  • 👤 Noriyuki Taguchi
  • 👤 Hiroshi Nomura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 08:58
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W74/019; H10W70/00; H10W70/60; H05; H05K; H05K3/00; H05K3/30; H10W70/67; H10W70/688; H10W74/014; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W90/701; H10W99/00; H05K3/10; H05K3/20; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7438; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W70/68; H10W70/682; H10W70/685; H10W72/00; H10W72/01; H10W72/0198; H10W72/071; H10W72/072; H10W72/073; H10W72/07302; H10W72/07304; H10W72/07331; H10W72/07336; H10W72/07337; H10W72/07351; H10W72/07353; H10W72/07355; H10W72/075; H10W72/07502; H10W72/07504; H10W72/30; H10W72/321; H10W72/325; H10W72/331; H10W72/334; H10W72/351; H10W72/352; H10W72/3528; H10W72/353; H10W72/354; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W74/15; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/736; H10W90/751; H10W90/754; H10W90/756

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 145 words
A process for the fabrication of semiconductor packages, which comprises the following steps: A) forming plural sets of wiring on one side of an insulating supporting member; B) removing said insulating supporting member at positions where external connection terminals for said wiring are to be formed, whereby through-holes for said external connection terminals are provided; C) mounting semiconductor devices on said insulating supporting member on which said plural sets of wiring have been formed, and then electrically connecting terminals of said semiconductor devices with said wiring, respectively; D) sealing said semiconductor devices with resin; E) forming, in said through-holes for said external connection terminals, said external connection terminals so that said external connection terminals are electrically connected to said wiring; and F) separating the resultant assembly into individual semiconductor packages, wherein a die-bonding tape is used for mounting said semiconductor devices in said step C.
Claim 2
Dependent Claim 145 words
A process for the fabrication of semiconductor packages, which comprises the following steps: A) forming plural sets of wiring on one side of an insulating supporting member; B) removing said insulating supporting member at positions where external connection terminals for said wiring are to be formed, whereby through-holes for said external connection terminals are provided; C) mounting semiconductor devices on said insulating supporting member on which said plural sets of wiring have been formed, and then electrically connecting terminals of said semiconductor devices with said wiring, respectively; D) sealing said semiconductor devices with resin; E) forming, in said through-holes for said external connection terminals, said external connection terminals so that said external connection terminals are electrically connected to said wiring; and F) separating the resultant assembly into individual semiconductor packages, wherein a die-bonding tape is used for mounting said semiconductor devices in said step C.
Claim 3
Dependent Claim 205 words
A process for the fabrication of semiconductor packages, which comprises the following steps: A) forming plural sets of wiring on one side of an insulating supporting member; B) removing said insulating supporting member at positions where external connection terminals for said wiring are to be formed, whereby through-holes for said external connection terminals are provided; C) mounting semiconductor devices on said insulating supporting member on which said plural sets of wiring have been formed, and then electrically connecting terminals of said semiconductor devices with said wiring, respectively; D) sealing said semiconductor devices with resin; E) forming, in said through-holes for said external connection terminals, said external connection terminals so that said external connection terminals are electrically connected to said wiring; and F) separating the resultant assembly into individual semiconductor packages, wherein each of said sets of wiring comprises more than one wiring having an inner connection section to be connected to a terminal of the semiconductor device and a mounting region on which the semiconductor device is to be mounted; and said step C is a step in which the semiconductor device is mounted on said mounting region of said wiring and said terminal of the semiconductor device is connected with said inner connection section.
Claim 4
Dependent Claim 205 words
A process for the fabrication of semiconductor packages, which comprises the following steps: A) forming plural sets of wiring on one side of an insulating supporting member; B) removing said insulating supporting member at positions where external connection terminals for said wiring are to be formed, whereby through-holes for said external connection terminals are provided; C) mounting semiconductor devices on said insulating supporting member on which said plural sets of wiring have been formed, and then electrically connecting terminals of said semiconductor devices with said wiring, respectively; D) sealing said semiconductor devices with resin; E) forming, in said through-holes for said external connection terminals, said external connection terminals so that said external connection terminals are electrically connected to said wiring; and F) separating the resultant assembly into individual semiconductor packages, wherein each of said sets of wiring comprises more than one wiring having an inner connection section to be connected to a terminal of the semiconductor device and a mounting region on which the semiconductor device is to be mounted; and said step C is a step in which the semiconductor device is mounted on said mounting region of said wiring and said terminal of the semiconductor device is connected with said inner connection section.
Claim 5
Dependent Claim 44 words
A process for the fabrication of semiconductor packages according to claim 2, wherein wire-bonding is used in said step 5C for connecting the semiconductor device with said inner connection section; and die-bonding material is used in said step 5C for mounting the semiconductor device.
Claim 6
Dependent Claim 20 words
A process for the fabrication of semiconductor packages according to claim 3, wherein said die-bonding material is a die-bonding tape.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-11-01 2003-05-03 2003-11-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-11-01 2007-05-03 2007-11-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-11-01 2011-05-03 2011-11-02 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag