US5973972A
Expired / Lapsed
US
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Precharge system for a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-11-04
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Granted: 1999-10-26
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Expires: 2016-11-04
Abstract
Abstract A method for precharging a bit line pair or data line pair in a semiconductor memory device includes generating a precharge pulse signal when a write enable line is deactivated at the beginning of a read cycle. The line pair is rapidly precharged by a pair of large transistors which turn on in response to the pulse signal. The pulse signal ends and turns of the transistors before a word line is enabled during the read cycle to prevent the large transistors from interfering with the bit sensing operation. A precharge circuit for precharging a bit line pair or data line pair in a semiconductor memory device includes a pulse generator having a delay circuit that determines the pulse width of a precharge pulse which is generated when a write enable line is deactivated. A write and precharge circuit includes two large transistors connected between a line pair and a power source that turn on and rapidly precharge the line pair during the precharge pulse. A third large transistor is connected between the lines of the line pair to equalize the voltages of the lines when the precharge pulse is generated.
Inventors
- 👤 Kook-Hwan Kwon
- 👤 Hee-Choul Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:40
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1048; G11C7/12; G11C7/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
196 words
A precharge system for a semiconductor memory device, the system comprising: a precharge circuit coupled to a line for precharging the line responsive to a pulse signal; and a pulse generating circuit coupled to the precharge circuit for generating the pulse signal responsive to a write signal; wherein the pulse generating circuit includes: a logic gate coupled to the precharge circuit for generating the pulse signal responsive to the activation of the write signal; and a delay circuit coupled to the logic gate for deactivating the pulse signal; and wherein: the delay circuit includes an input terminal coupled to receive the write signal and an output terminal; the logic gate is a NOR gate having a first input terminal coupled to receive the write signal, a second input terminal, and an output terminal; and the pulse generating circuit further includes: a first inverter having an input terminal coupled to the output terminal of the delay circuit and an output terminal coupled to the second input terminal of the NOR gate; and a second inverter having an input terminal coupled to the output terminal of the NOR gate and an output terminal coupled to the precharge circuit.
Claim 2
Dependent Claim
196 words
A precharge system for a semiconductor memory device, the system comprising: a precharge circuit coupled to a line for precharging the line responsive to a pulse signal; and a pulse generating circuit coupled to the precharge circuit for generating the pulse signal responsive to a write signal; wherein the pulse generating circuit includes: a logic gate coupled to the precharge circuit for generating the pulse signal responsive to the activation of the write signal; and a delay circuit coupled to the logic gate for deactivating the pulse signal; and wherein: the delay circuit includes an input terminal coupled to receive the write signal and an output terminal; the logic gate is a NOR gate having a first input terminal coupled to receive the write signal, a second input terminal, and an output terminal; and the pulse generating circuit further includes: a first inverter having an input terminal coupled to the output terminal of the delay circuit and an output terminal coupled to the second input terminal of the NOR gate; and a second inverter having an input terminal coupled to the output terminal of the NOR gate and an output terminal coupled to the precharge circuit.
Claim 3
Dependent Claim
209 words
A precharge system for a semiconductor memory device, the system comprising: a pulse generating circuit for generating a pulse signal responsive to a write signal, wherein the pulse generating circuit activates the pulse signal when the write signal is deactivated and deactivates the pulse signal a predetermined amount of time thereafter; a first MOS precharge transistor coupled between a first line and a power supply terminal for precharging the first line when the write signal is deactivated; a second MOS precharge transistor coupled between a second line and the power supply terminal for precharging the second line when the write signal is deactivated; a third MOS precharge transistor coupled between the first line and the power supply terminal for precharging the first line when the pulse signal is activated; and a fourth MOS precharge transistor coupled between the second line and the power supply terminal for precharging the second line when the pulse signal is activated; wherein the third and fourth MOS transistors are relatively larger than the first and second MOS transistors so as to precharge the first and second lines faster than the first and second MOS transistors; and whereby the first, second, third, and fourth MOS transistors all precharge simultaneously while the pulse signal is activated.
Claim 4
Dependent Claim
209 words
A precharge system for a semiconductor memory device, the system comprising: a pulse generating circuit for generating a pulse signal responsive to a write signal, wherein the pulse generating circuit activates the pulse signal when the write signal is deactivated and deactivates the pulse signal a predetermined amount of time thereafter; a first MOS precharge transistor coupled between a first line and a power supply terminal for precharging the first line when the write signal is deactivated; a second MOS precharge transistor coupled between a second line and the power supply terminal for precharging the second line when the write signal is deactivated; a third MOS precharge transistor coupled between the first line and the power supply terminal for precharging the first line when the pulse signal is activated; and a fourth MOS precharge transistor coupled between the second line and the power supply terminal for precharging the second line when the pulse signal is activated; wherein the third and fourth MOS transistors are relatively larger than the first and second MOS transistors so as to precharge the first and second lines faster than the first and second MOS transistors; and whereby the first, second, third, and fourth MOS transistors all precharge simultaneously while the pulse signal is activated.
Claim 5
Independent Claim
145 words
A method for precharging a first bitline and a second bitline forming a bitline pair in a semiconductor memory device, the method comprising: precharging the first bitline with a first MOS precharge transistor whenever a write signal is deactivated; precharging the second bitline with a second MOS precharge transistor whenever the write signal is deactivated; precharging the first bitline with a third MOS precharge transistor for a predetermined time after the write signal is deactivated; and precharging the second bitline with a fourth MOS precharge transistor for a predetermined time after the write signal is deactivated; wherein the third and fourth MOS transistors are relatively larger than the first and second MOS transistors so as to precharge the first and second lines faster than the first and second MOS transistors; and whereby the third and fourth MOS transistors automatically turned off after the predetermined time.
Claim 6
Independent Claim
145 words
A method for precharging a first bitline and a second bitline forming a bitline pair in a semiconductor memory device, the method comprising: precharging the first bitline with a first MOS precharge transistor whenever a write signal is deactivated; precharging the second bitline with a second MOS precharge transistor whenever the write signal is deactivated; precharging the first bitline with a third MOS precharge transistor for a predetermined time after the write signal is deactivated; and precharging the second bitline with a fourth MOS precharge transistor for a predetermined time after the write signal is deactivated; wherein the third and fourth MOS transistors are relatively larger than the first and second MOS transistors so as to precharge the first and second lines faster than the first and second MOS transistors; and whereby the third and fourth MOS transistors automatically turned off after the predetermined time.
References Cited (Backward Citations)
US5579256A
Cited
US5506805A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-25 | 2003-04-26 | 2003-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-25 | 2007-04-26 | 2007-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-25 | 2011-04-26 | 2011-10-26 | $7700.00 | Window Closed / Lapsed |