Operational amplifier push-pull output stage with low quiescent current

Claim 2

An output circuit comprising: (a) an input stage receiving an input voltage and producing first and second signals in response to the input voltage; (b) an output stage including an NPN pull-up transistor and an NPN pull-down transistor, a base of the NPN pull-up transistor being coupled to receive the first signal, an emitter of the NPN pull-up transistor being coupled by an output conductor to a collector of the NPN pull-down transistor, a base of the NPN pull-down transistor being coupled to receive the second signal, and an emitter of the NPN pull-down transistor being coupled to a reference voltage conductor; (c) a feedback stage including a first sensing circuit coupled to the NPN pull-up transistor and producing a third signal representing a collector current of the NPN pull-up transistor, a second sensing circuit coupled to the NPN pull-down transistor and producing a fourth signal representing a collector current of the NPN pull-down transistor, a combining circuit receiving the third and fourth signals to produce an error signal representing the larger of the third and fourth signals, and an error amplifier receiving the error signal to produce a feedback signal regulating the first and second signals to establish a stable quiescent current in the one of the pull-up transistor and the NPN pull-down transistor having the lowest collector current.

Claim 3

An output circuit comprising: (a) an input stage including a first NPN transistor, a PNP current source transistor, and a first constant current source, the PNP current source transistor having an emitter coupled to a first supply voltage conductor and a collector coupled by a first conductor to a collector of the first NPN transistor, a base of the first NPN transistor receiving an input voltage, the first constant current source being coupled by a second conductor to an emitter of the first NPN transistor; (b) an output stage including an NPN pull-up transistor and an NPN pull-down transistor, a base of the NPN pull-up transistor being coupled to the first conductor, an emitter of the NPN pull-up transistor being coupled by an output conductor to a collector of the NPN pull-down transistor, a base of the NPN pull-down transistor being coupled to the second conductor, and an emitter of the NPN pull-down transistor being coupled to a second reference voltage conductor; (c) a feedback stage including a first sensing circuit coupled to the first conductor and the output conductor and producing a first signal representing a collector current of the NPN pull-up transistor, a second sensing circuit coupled to the second conductor and the second reference voltage conductor and producing a second signal representing a collector current of the NPN pull-down transistor, a wire ORing circuit receiving the first and second signals to produce a wire ORed error signal representing the larger of the first and second signals, and an error amplifier receiving the wire ORed error signal to produce a feedback signal controlling a base of the PNP current source transistor to establish a stable quiescent current in the one of the NPN pull-up transistor and the NPN pull-down transistor having the lowest collector current.

Claim 4

An output circuit comprising: (a) an input stage including a first NPN transistor, a PNP current source transistor, and a first constant current source, the PNP current source transistor having an emitter coupled to a first supply voltage conductor and a collector coupled by a first conductor to a collector of the first NPN transistor, a base of the first NPN transistor receiving an input voltage, the first constant current source being coupled by a second conductor to an emitter of the first NPN transistor; (b) an output stage including an NPN pull-up transistor and an NPN pull-down transistor, a base of the NPN pull-up transistor being coupled to the first conductor, an emitter of the NPN pull-up transistor being coupled by an output conductor to a collector of the NPN pull-down transistor, a base of the NPN pull-down transistor being coupled to the second conductor, and an emitter of the NPN pull-down transistor being coupled to a second reference voltage conductor; (c) a feedback stage including a first sensing circuit coupled to the first conductor and the output conductor and producing a first signal representing a collector current of the NPN pull-up transistor, a second sensing circuit coupled to the second conductor and the second reference voltage conductor and producing a second signal representing a collector current of the NPN pull-down transistor, a wire ORing circuit receiving the first and second signals to produce a wire ORed error signal representing the larger of the first and second signals, and an error amplifier receiving the wire ORed error signal to produce a feedback signal controlling a base of the PNP current source transistor to establish a stable quiescent current in the one of the NPN pull-up transistor and the NPN pull-down transistor having the lowest collector current.

Claim 5

The output circuit of claim 2 wherein an output of the error amplifier is connected to the base of the PNP current source transistor.

Claim 6

The output circuit of claim 2 wherein an inverting input of the error amplifier receives the wire ORed error signal and a non-inverting input of the error amplifier receives a reference voltage, the feedback signal stabilizing the quiescent current to a value determined by the reference voltage.

Claim 7

The output circuit of claim 4 wherein the wire ORing circuit includes second and third NPN transistors having their emitters coupled to a third conductor conducting the wire ORed error signal, a base of the second NPN transistor receiving the first signal, a base of the third NPN transistor receiving the second signal.

Claim 8

The output circuit of claim 5 wherein (a) the first sensing circuit includes a fourth NPN transistor having a base coupled to the first conductor, a first resistor coupled between the output conductor and an emitter of the fourth NPN transistor, and a second resistor coupled between the first reference voltage conductor and a collector of the fourth NPN transistor, a fourth conductor coupling the first signal from the collector of the fourth NPN transistor to the base of the second NPN transistor; and (b) the second sensing circuit includes a fifth NPN transistor having a base coupled to the second conductor, a third resistor coupled between the output conductor and the second reference voltage conductor, and a fourth resistor coupled between the first reference voltage conductor and a collector of the fifth NPN transistor, a fifth conductor coupling the second signal from the collector of the fifth NPN transistor to the base of the third NPN transistor.

Claim 9

The output circuit of claim 4 including a reference circuit including a reference resistor coupled between the non-inverting input of the error amplifier and the first reference voltage conductor, and a second constant current source coupled between the non-inverting input of the error amplifier and the second reference voltage conductor.

Claim 10

The output circuit of claim 5 wherein the wire Oring circuit includes a second constant current source coupled between the second supply voltage conductor and the third conductor.

Claim 13

An operational amplifier comprising: (a) a gain stage having an inverting input for receiving an input signal and a non-inverting input, and an output producing an intermediate signal; (b) an output circuit including: i. an input stage receiving an input voltage and producing first and second signals in response to the input voltage; ii. an output stage including an NPN pull-up transistor and an NPN pull-down transistor, a base of the NPN pull-up transistor being coupled to receive the first signal, an emitter of the NPN pull-up transistor being coupled by an output conductor to a collector of the NPN pull-down transistor, a base of the NPN pull-down transistor being coupled to receive the second signal, and an emitter of the NPN pull-down transistor being coupled to a second reference voltage conductor; iii. a feedback stage including a first sensing circuit coupled to the NPN pull-up transistor and producing a third signal representing a collector current of the NPN pull-up transistor, a second sensing circuit coupled to the NPN pull-down transistor and producing a fourth signal representing a collector current of the NPN pull-down transistor, a combining circuit receiving the third and fourth signals to produce an error signal representing the larger of the third and fourth signals, and an error amplifier receiving the error signal to produce a feedback signal regulating the first and second signals to establish a stable quiescent current in the one of the pull-up transistor and the NPN pull-down transistor having the lowest collector current.

Claim 14

An operational amplifier comprising: (a) a gain stage having an inverting input for receiving an input signal and a non-inverting input, and an output producing an intermediate signal; (b) an output circuit including: i. an input stage receiving an input voltage and producing first and second signals in response to the input voltage; ii. an output stage including an NPN pull-up transistor and an NPN pull-down transistor, a base of the NPN pull-up transistor being coupled to receive the first signal, an emitter of the NPN pull-up transistor being coupled by an output conductor to a collector of the NPN pull-down transistor, a base of the NPN pull-down transistor being coupled to receive the second signal, and an emitter of the NPN pull-down transistor being coupled to a second reference voltage conductor; iii. a feedback stage including a first sensing circuit coupled to the NPN pull-up transistor and producing a third signal representing a collector current of the NPN pull-up transistor, a second sensing circuit coupled to the NPN pull-down transistor and producing a fourth signal representing a collector current of the NPN pull-down transistor, a combining circuit receiving the third and fourth signals to produce an error signal representing the larger of the third and fourth signals, and an error amplifier receiving the error signal to produce a feedback signal regulating the first and second signals to establish a stable quiescent current in the one of the pull-up transistor and the NPN pull-down transistor having the lowest collector current.

Claim 15

An operational amplifier comprising: (a) a gain stage having an inverting input for receiving an input signal and a non-inverting input, and an output producing an intermediate signal; (b) an output stage including i. an input stage including a first NPN transistor, a PNP current source transistor, and a first constant current source, the PNP current source transistor having an emitter coupled to a first supply voltage conductor and a collector coupled by a first conductor to a collector of the first NPN transistor, a base of the first NPN transistor receiving an input voltage, the first constant current source being coupled by a second conductor to an emitter of the first NPN transistor; ii. an output stage including an NPN pull-up transistor and an NPN pull-down transistor, a base of the NPN pull-up transistor being coupled to the first conductor, an emitter of the NPN pull-up transistor being coupled by an output conductor to a collector of the NPN pull-down transistor, a base of the NPN pull-down transistor being coupled to the second conductor, and an emitter of the NPN pull-down transistor being coupled to a second reference voltage conductor; iii. a feedback stage including a first sensing circuit coupled to the first conductor and the output conductor and producing a first signal representing a collector current of the NPN pull-up transistor, a second sensing circuit coupled to the second conductor and the second reference voltage conductor and producing a second signal representing a collector current of the NPN pull-down transistor, a wire ORing circuit receiving the first and second signals to produce a wire ORed error signal representing the larger of the first and second signals, and an error amplifier receiving the wire ORed error signal to produce a feedback signal controlling a base of the PNP current source transistor to establish a stable quiescent current in the one of the NPN pull-up transistor and the NPN pull-down transistor having the lowest collector current.

Claim 16

An operational amplifier comprising: (a) a gain stage having an inverting input for receiving an input signal and a non-inverting input, and an output producing an intermediate signal; (b) an output stage including i. an input stage including a first NPN transistor, a PNP current source transistor, and a first constant current source, the PNP current source transistor having an emitter coupled to a first supply voltage conductor and a collector coupled by a first conductor to a collector of the first NPN transistor, a base of the first NPN transistor receiving an input voltage, the first constant current source being coupled by a second conductor to an emitter of the first NPN transistor; ii. an output stage including an NPN pull-up transistor and an NPN pull-down transistor, a base of the NPN pull-up transistor being coupled to the first conductor, an emitter of the NPN pull-up transistor being coupled by an output conductor to a collector of the NPN pull-down transistor, a base of the NPN pull-down transistor being coupled to the second conductor, and an emitter of the NPN pull-down transistor being coupled to a second reference voltage conductor; iii. a feedback stage including a first sensing circuit coupled to the first conductor and the output conductor and producing a first signal representing a collector current of the NPN pull-up transistor, a second sensing circuit coupled to the second conductor and the second reference voltage conductor and producing a second signal representing a collector current of the NPN pull-down transistor, a wire ORing circuit receiving the first and second signals to produce a wire ORed error signal representing the larger of the first and second signals, and an error amplifier receiving the wire ORed error signal to produce a feedback signal controlling a base of the PNP current source transistor to establish a stable quiescent current in the one of the NPN pull-up transistor and the NPN pull-down transistor having the lowest collector current.

Claim 17

The operational amplifier of claim 11 wherein an output of the error amplifier is connected to the base of the PNP current source transistor.

Claim 18

The operational amplifier of claim 11 wherein an inverting input of the error amplifier receives the wire ORed error signal and a non-inverting input of the error amplifier receives a reference voltage, the feedback signal stabilizing the quiescent current to a value determined by the reference voltage.

Claim 19

The operational amplifier of claim 13 wherein the wire ORing circuit includes second and third NPN transistors having their emitters coupled to a third conductor conducting the wire ORed error signal, a base of the second NPN transistor receiving the first signal, a base of the third NPN transistor receiving the second signal.

Claim 20

The operational amplifier of claim 14 wherein (a) the first sensing circuit includes a fourth NPN transistor having a base coupled to the first conductor, a first resistor coupled between the output conductor and an emitter of the fourth NPN transistor, and a second resistor coupled between the first reference voltage conductor and a collector of the fourth NPN transistor, a fourth conductor coupling the first signal from the collector of the fourth NPN transistor to the base of the second NPN transistor; and (b) the second sensing circuit includes a fifth NPN transistor having a base coupled to the second conductor, a third resistor coupled between the output conductor and the second reference voltage conductor, and a fourth resistor coupled between the first reference voltage conductor and a collector of the fifth NPN transistor, a fifth conductor coupling the second signal from the collector of the fifth NPN transistor to the base of the third NPN transistor.

Claim 21

The operational amplifier of claim 13 including a reference circuit including a reference resistor coupled between the non-inverting input of the error amplifier and the first reference voltage conductor, and a second constant current source coupled between the non-inverting input of the error amplifier and the second reference voltage conductor.

Claim 22

The operational amplifier of claim 11 including a feedback circuit coupled between the output and the inverting input of the operational amplifier to maintain the output voltage at a level corresponding to the input signal despite variations in an output current.

Claim 25

An output circuit comprising: (a) an input stage receiving an input voltage and producing first and second signals in response to the input voltage; (b) an output stage including a pull-up transistor and a pull-down transistor, a control electrode of the pull-up transistor being coupled to receive the first signal, an first electrode of the pull-up transistor being coupled by an output conductor to a second electrode of the pull-down transistor, a control electrode of the pull-down transistor being coupled to receive the second signal, and a first electrode of the pull-down transistor being coupled to a second reference voltage conductor; (c) a feedback stage including a first sensing circuit coupled to the pull-up transistor 1 and producing a third signal representing a second electrode current of the pull-up transistor, a second sensing circuit coupled to the pull-down transistor and producing a fourth signal representing a second electrode current of the pull-down transistor, a combining circuit receiving the third and fourth signals to produce an error signal representing the larger of the third and fourth signals, and an error amplifier receiving the error signal to produce a feedback signal regulating the first and second signals to establish a stable quiescent current in the one of the pull-up transistor and the pull-down transistor having the lowest second electrode current.

Claim 26

An output circuit comprising: (a) an input stage receiving an input voltage and producing first and second signals in response to the input voltage; (b) an output stage including a pull-up transistor and a pull-down transistor, a control electrode of the pull-up transistor being coupled to receive the first signal, an first electrode of the pull-up transistor being coupled by an output conductor to a second electrode of the pull-down transistor, a control electrode of the pull-down transistor being coupled to receive the second signal, and a first electrode of the pull-down transistor being coupled to a second reference voltage conductor; (c) a feedback stage including a first sensing circuit coupled to the pull-up transistor 1 and producing a third signal representing a second electrode current of the pull-up transistor, a second sensing circuit coupled to the pull-down transistor and producing a fourth signal representing a second electrode current of the pull-down transistor, a combining circuit receiving the third and fourth signals to produce an error signal representing the larger of the third and fourth signals, and an error amplifier receiving the error signal to produce a feedback signal regulating the first and second signals to establish a stable quiescent current in the one of the pull-up transistor and the pull-down transistor having the lowest second electrode current.