Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
387 words
An addressable array of non-volatile ferromagnetic random access annular memory elements, comprising: a first sense row in the array of at least two non-volatile ferromagnetic random access memory elements; each of said non-volatile ferromagnetic random access memory elements having upper and lower surfaces and including: (i) at least a first ferromagnetic ring and a second ferromagnetic ring, wherein one of said ferromagnetic rings is hard or antiferromagnetically-pinned and the other ferromagnetic ring is magnetically softer than said hard or antiferromagnetically-pinned ring; and (ii) a non-magnetic layer sandwiched between said first and second ferromagnetic rings; a first conducting lead made up of a series of conductive strips along the first sense row of the array, each of said strips connects two adjacent memory elements at either their upper surface or at their lower surfaces, except at the ends of a sense row, said strips of the sense line being staggered so that each memory element is connected through its upper surface to the memory element on one side, and through its lower surface to the memory element on the other side, whereby a meandering conductive pathway through the sense line from one side of the array to the other in series is formed containing as many elements as desired; a first word line transverse to said first sense row, and made up of a series of wires passing in magnetic field producing proximity to the memory elements along a column of the array and not being in electrical contact with the memory elements; a second conducting lead made up of a series of conductive strips along the first word line of the array, each of said strips connects two adjacent wires at either their top contacts or at their bottom contacts, said strips of the word line are staggered so that each wire is connected through its top contact to the wire on one side, and through its bottom contact to the wire on the other side, whereby a meandering conductive pathway through the word line from one side of the array to the other in series is formed; said first word line defining a conductive path for flowing a current through the wire passing in magnetic field producing proximity to the memory elements, and said conductive paths being perpendicular to closed magnetic circuits in said ferromagnetic rings.
Claim 2
Dependent Claim
387 words
An addressable array of non-volatile ferromagnetic random access annular memory elements, comprising: a first sense row in the array of at least two non-volatile ferromagnetic random access memory elements; each of said non-volatile ferromagnetic random access memory elements having upper and lower surfaces and including: (i) at least a first ferromagnetic ring and a second ferromagnetic ring, wherein one of said ferromagnetic rings is hard or antiferromagnetically-pinned and the other ferromagnetic ring is magnetically softer than said hard or antiferromagnetically-pinned ring; and (ii) a non-magnetic layer sandwiched between said first and second ferromagnetic rings; a first conducting lead made up of a series of conductive strips along the first sense row of the array, each of said strips connects two adjacent memory elements at either their upper surface or at their lower surfaces, except at the ends of a sense row, said strips of the sense line being staggered so that each memory element is connected through its upper surface to the memory element on one side, and through its lower surface to the memory element on the other side, whereby a meandering conductive pathway through the sense line from one side of the array to the other in series is formed containing as many elements as desired; a first word line transverse to said first sense row, and made up of a series of wires passing in magnetic field producing proximity to the memory elements along a column of the array and not being in electrical contact with the memory elements; a second conducting lead made up of a series of conductive strips along the first word line of the array, each of said strips connects two adjacent wires at either their top contacts or at their bottom contacts, said strips of the word line are staggered so that each wire is connected through its top contact to the wire on one side, and through its bottom contact to the wire on the other side, whereby a meandering conductive pathway through the word line from one side of the array to the other in series is formed; said first word line defining a conductive path for flowing a current through the wire passing in magnetic field producing proximity to the memory elements, and said conductive paths being perpendicular to closed magnetic circuits in said ferromagnetic rings.
Claim 3
Dependent Claim
25 words
An addressable array according to claim 1, wherein the non-magnetic layer sandwiched between the first and second ferromagnetic rings in the memory element is conductive.
Claim 4
Dependent Claim
35 words
An addressable array according to claim 2, wherein the memory elements are annular and have an open core and wherein the wires of the word line pass through the open cores of the memory elements.
Claim 5
Dependent Claim
20 words
An addressable array according to claim 2, wherein the wires of the word line pass adjacent to the memory elements.
Claim 6
Dependent Claim
21 words
An addressable array according to claim 4, wherein each wire of the word line passes adjacent to a single memory element.
Claim 7
Dependent Claim
20 words
An addressable array according to claim 4, wherein each wire of the word line passes between two adjacent memory elements.
Claim 8
Dependent Claim
188 words
An addressable array according to claim 1, further comprising: a first bit line parallel to said first sense row, and made up of a series of wires passing in magnetic field producing proximity to the memory elements along a column of the array and not being in electrical contact with the memory elements; a third conducting lead made up of a series of conductive strips along the first bit line of the array, each of said strips connects two adjacent wires at either their top contacts or at their bottom contacts, said strips of the bit line are staggered so that each wire is connected through its top contact to the wire on one side, and through its bottom contact to the wire on the other side, whereby a meandering conductive pathway through the bit line from one side of the array to the other in series is formed; said first bit line defining a conductive path for flowing a current through the wire passing in magnetic field producing proximity to the memory elements, and said conductive paths being perpendicular to closed magnetic circuits in said ferromagnetic rings.
Claim 9
Dependent Claim
25 words
An addressable array according to claim 7, wherein the non-magnetic layer sandwiched between the first and second ferromagnetic rings in the memory element is conductive.
Claim 10
Dependent Claim
35 words
An addressable array according to claim 8, wherein the memory elements are annular and have an open core and wherein the wires of the word line pass through the open cores of the memory elements.
Claim 11
Dependent Claim
20 words
An addressable array according to claim 8, wherein the wires of the word line pass adjacent to the memory elements.
Claim 12
Dependent Claim
21 words
An addressable array according to claim 10, wherein each wire of the word line passes adjacent to a single memory element.
Claim 13
Dependent Claim
20 words
An addressable array according to claim 10, wherein each wire of the word line passes between two adjacent memory elements.
Claim 14
Dependent Claim
20 words
An addressable array according to claim 8, wherein the wires of the bit line pass adjacent to the memory elements.
Claim 15
Dependent Claim
21 words
An addressable array according to claim 13, wherein each wire of the bit line passes adjacent to a single memory element.
Claim 16
Dependent Claim
20 words
An addressable array according to claim 13, wherein each wire of the bit line passes between two adjacent memory elements.
Claim 17
Dependent Claim
25 words
An addressable array according to claim 7, wherein the non-magnetic layer sandwiched between the first and second ferromagnetic rings in the memory element is insulative.
Claim 18
Dependent Claim
20 words
An addressable array according to claim 16, wherein the wires of the bit line pass adjacent to the memory elements.
Claim 19
Dependent Claim
21 words
An addressable array according to claim 17, wherein each wire of the bit line passes adjacent to a single memory element.
Claim 20
Dependent Claim
20 words
An addressable array according to claim 17, wherein each wire of the bit line passes between two adjacent memory elements.
Claim 21
Dependent Claim
20 words
An addressable array according to claim 16, wherein the non-volatile ferromagnetic random access memory element is a magnetic tunnel junction.