Metal salicide process employing ion metal plasma deposition

Claim 1

A method for forming self-aligned metal silicide layers on an MOS transistor structure comprising the steps of: providing an MOS transistor structure including: a silicon substrate of a first conductivity type; a thin gate oxide layer disposed on the silicon substrate, the thin gate oxide layer having two sides; a polysilicon gate overlying the thin gate oxide layer, the polysilicon gate having two sides; source and drain regions of a second conductivity type in the silicon substrate; a first gate sidewall spacer overlying the source region and abutting one side of the polysilicon gate and the thin gate oxide layer, the first gate sidewall spacer having a lateral surface; and a second gate sidewall spacer overlying the drain region and abutting the other side of the polysilicon gate and the thin oxide layer opposite the first gate sidewall spacer, the second gate sidewall spacer having a lateral surface; depositing a metal layer on the source region, the drain region, the polysilicon gate and the first and second gate sidewall spacers, using an ion metal plasma process with a ratio of the metal layer thickness on the lateral surface of the first and second gate sidewall spacers to the metal layer thickness on the polysilicon gate being less than 0.2; reacting metal in the metal layer with silicon in the source region, the drain region and the polysilicon gate to yield self-aligned metal silicide layers on the source region, drain region and polysilicon gate; and removing any unreacted metal.

Claim 2

A method for forming self-aligned metal silicide layers on an MOS transistor structure comprising the steps of: providing an MOS transistor structure including: a silicon substrate of a first conductivity type; a thin gate oxide layer disposed on the silicon substrate, the thin gate oxide layer having two sides; a polysilicon gate overlying the thin gate oxide layer, the polysilicon gate having two sides; source and drain regions of a second conductivity type in the silicon substrate; a first gate sidewall spacer overlying the source region and abutting one side of the polysilicon gate and the thin gate oxide layer, the first gate sidewall spacer having a lateral surface; and a second gate sidewall spacer overlying the drain region and abutting the other side of the polysilicon gate and the thin oxide layer opposite the first gate sidewall spacer, the second gate sidewall spacer having a lateral surface; depositing a metal layer on the source region, the drain region, the polysilicon gate and the first and second gate sidewall spacers, using an ion metal plasma process with a ratio of the metal layer thickness on the lateral surface of the first and second gate sidewall spacers to the metal layer thickness on the polysilicon gate being less than 0.2; reacting metal in the metal layer with silicon in the source region, the drain region and the polysilicon gate to yield self-aligned metal silicide layers on the source region, drain region and polysilicon gate; and removing any unreacted metal.