Hardware-software co-simulation system, hardware-software co-simulation method, and computer-readable memory containing a hardware-software co-simulation program

Claim 2

A hardware/software co-simulation system comprising: a hardware verification module for performing simulation for hardware verification with input from an RT-level processor model and an RT-level hardware description; an abstraction module for abstracting from the RT-level hardware description on a processor input/output instruction operation level and for generating an abstracted description describing an instruction level hardware description, and a software verification module for performing simulation for software verification with input from an instruction-level processor model and said abstracted description.

Claim 3

A hardware/software co-simulation system according to claim 1 wherein said abstraction module abstracts one process from the RT-level hardware description on the processor input/output operation level to generate said abstracted description.

Claim 4

A hardware/software co-simulation system according to claim 1 wherein said abstraction module comprises: a state transition creating section for creating a state transition graph by analyzing the RT-level hardware description; an ordered sequence creating section for creating an ordered sequence by sequencing a plurality of states into a row with an initial state of said state transition graphs first: a loop disconnecting section for disconnecting a loop which is in said state transition graph and which includes input/output operations; a process forming section for sequencing operation descriptions of each state according to the ordered sequence and deleting internal signals to form one process; and an abstracted description generating section for generating said abstracted description by inserting at least one statement which sets a flag at a loop disconnection location and at least one statement which skips subsequent processing.

Claim 5

A hardware/software co-simulation system according to claim 3 wherein said loop disconnecting section determines that the input/output operations are included when there is at least one signal assignment statement with an external input pin on a right-hand side or with an external output pin on a left-hand side.

Claim 6

A hardware/software co-simulation system according to claim 3, further comprising an iteration statement inserting section for inserting an iteration statement at a location where the loop is not disconnected.

Claim 7

A hardware/software co-simulation system according to claim 1 wherein said abstraction module abstracts a plurality of processes from the RT-level hardware description on a processor input/output operation level to generate said abstracted description.

Claim 8

A hardware/software co-simulation system according to claim 1 wherein said abstraction module comprises: a state transition graph creating section for creating a state transition graph by analyzing the RT-level hardware description; an ordered sequence creating section for creating an ordered sequence by sequencing a plurality of states into a row with an initial state of said state transition graph first; a determining section for determining whether a state transition going back toward a beginning of said created ordered sequence is to be deleted or not; a dividing section for dividing the ordered sequence into a plurality of subdivisions according to a destination state of said state transition determined not to be deleted; and an abstracted description generating section for generating said abstracted description by forming an operation description of each of said plurality of subdivisions into one process.

Claim 9

A hardware/software co-simulation system according to claim 7 wherein said determining section determines that the state transition going backward is not to be deleted when a closed loop formed by the state transition going backward includes input/output operations and that the state transition going backward is to be deleted when the closed loop does not include input/output operations.

Claim 10

A hardware/software co-simulation method comprising the steps of: performing simulation for hardware verification with input from an RT-level processor model and an RT-level hardware description; abstracting from the RT-level hardware description on a processor input/output instruction operation level and for generating an abstracted description describing an instruction-level hardware description; and performing simulation for software verification with input from an instruction-level processor model and said abstracted description.

Claim 11

A hardware/software co-simulation method comprising the steps of: performing simulation for hardware verification with input from an RT-level processor model and an RT-level hardware description; abstracting from the RT-level hardware description on a processor input/output instruction operation level and for generating an abstracted description describing an instruction-level hardware description; and performing simulation for software verification with input from an instruction-level processor model and said abstracted description.

Claim 12

A hardware/software co-simulation method according to claim 9 wherein said abstracting step abstracts one process from the RT-level hardware description on the processor input/output operation level to generate said abstracted description.

Claim 13

A hardware/software co-simulation method according to claim 9 wherein said abstracting step comprises the steps of: creating a state transition graph by analyzing the RT-level hardware description; creating an ordered sequence by sequencing a plurality of states into a row with an initial state of said state transition graph first; disconnecting a loop which is in said state transition graph and which includes input/output operations; a process forming section for sequencing operation descriptions of each state according to the ordered sequence and deleting internal signals to form one process; and generating said abstracted description by inserting at least one statement which sets a flag at a loop disconnection location and at least one statement which skips subsequent processing.

Claim 14

A hardware/software co-simulation method according to claim 11 wherein said loop disconnecting step determines that the input/output operations are included when there is at least one signal assignment statement with an external input pin on a right-hand side or with an external output pin on a left-hand side.

Claim 15

A hardware/software co-simulation method according to claim 11, further comprising the step of inserting an iteration statement at a location where the loop is not disconnected.

Claim 16

A hardware/software co-simulation method according to claim 9 wherein said abstracting step abstracts a plurality of processes from the RT-level hardware description on a processor input/output operation level to generate said abstracted description.

Claim 17

A hardware/software co-simulation method according to claim 9 wherein said abstracting step comprises the steps of: creating a state transition graph by analyzing the RT-level hardware description; creating an ordered sequence by sequencing a plurality of states into a row with an initial state of said state transition graph first; determining whether a state transition going back toward a beginning of said created ordered sequence is to be deleted or not; dividing the ordered sequence into a plurality of subdivisions according to a destination state of said state transition determined not to be deleted; and generating said abstracted description by forming an operation description of each of said plurality of subdivisions into one process.

Claim 18

A hardware/software co-simulation method according to claim 15 wherein said determining step determines that the state transition going backward is not to be deleted when a closed loop formed by the state transition going backward includes input/output operations and that the state transition going backward is to be deleted when the closed loop does not include input/output operations.

Claim 19

A computer-readable memory having stored therein a hardware/software co-simulation program, said program comprising: a hardware verification process for performing simulation for hardware verification with input from an RT-level processor model and an RT-level hardware description; an abstraction process for abstracting from the RT-level hardware description on a processor input/output instruction operation level and for generating an abstracted description describing an instruction-level hardware description; and a software verification process for performing simulation for software verification with input from an instruction-level processor model and said abstracted description.

Claim 20

A computer-readable memory having stored therein a hardware/software co-simulation program, said program comprising: a hardware verification process for performing simulation for hardware verification with input from an RT-level processor model and an RT-level hardware description; an abstraction process for abstracting from the RT-level hardware description on a processor input/output instruction operation level and for generating an abstracted description describing an instruction-level hardware description; and a software verification process for performing simulation for software verification with input from an instruction-level processor model and said abstracted description.

Claim 21

A computer-readable memory having stored therein a hardware/software co-simulation program according to claim 17 wherein said abstraction process abstracts one process from the RT-level hardware description on the processor input/output operation level to generate said abstracted description.

Claim 22

A computer-readable memory having stored therein a hardware/software co-simulation program according to claim 17 wherein said abstraction process comprises: a state transition creating process for creating a state transition graph by analyzing the RT-level hardware description; an ordered sequence creating process for creating an ordered sequence by sequencing a plurality of states into a row with an initial state of said state transition graph first; a loop disconnecting process for disconnecting a loop which is in said state transition graph and which includes input/output operations; a process forming process for sequencing operation descriptions of each state according to the ordered sequence and deleting internal signals to form one process; and an abstracted description generating process for generating said abstracted description by inserting at least one statement which sets a flag at a loop disconnection location and at least one statement which skips subsequent processing.

Claim 23

A computer-readable memory having stored therein a hardware/software co-simulation program according to claim 19 wherein said loop disconnecting process determines that the input/output operations are included when there is at least one signal assignment statement with an external input pin on a right-hand side or with an external output pin on a left-hand side.

Claim 24

A computer-readable memory having stored therein a hardware/software co-simulation program according to claim 19, further comprising an iteration statement inserting process for inserting an iteration statement at a location where the loop is not disconnected.

Claim 25

A computer-readable memory having stored therein a hardware/software co-simulation program according to claim 17 wherein said abstraction process abstracts a plurality of processes from the RT-level hardware description on a processor input/output operation level to generate said abstracted description.

Claim 26

A computer-readable memory having stored therein a hardware/software co-simulation program according to claim 17 wherein said abstraction process comprises: a state transition graph creating process for creating a state transition graph by analyzing the RT-level hardware description; an ordered sequence creating process for creating an ordered sequence by sequencing a plurality of states into a row with an initial state of said state transition graph first; a determining process for determining whether a state transition going back toward a beginning of said created ordered sequence is to be deleted or not; a dividing process for dividing the ordered sequence into a plurality of subdivisions according to a destination state of said state transition determined not to be deleted; and an abstracted description generating process for generating said abstracted description by forming an operation description of each of said plurality of subdivisions into one process.

Claim 27

A computer-readable memory having stored therein a hardware/software co-simulation program according to claim 23 wherein said determining process determines that the state transition going backward is not to be deleted when a closed loop formed by the state transition going backward includes input/output operations and that the state transition going backward is to be deleted when the closed loop does not include input/output operations.